Table 12.9 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (2)-2; Table 12.10 Relationship Between Bsz1, 0, A2/3Row1, 0, And - Renesas HD6417641 Hardware Manual

Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(2)-2
BSZ A2/3
1, 0 ROW
1, 0
11 (32 bits) 00 (11 bits)
Output Pin of Row Address
This LSI Output Cycle
A17 A27
A16 A26
A15 A25*
A14 A24*
A13 A23
A12 A22
A11 A21
A10 A20*
A9 A19
A8 A18
A7 A17
A6 A16
A5 A15
A4 A14
A3 A13
A2 A12
A1 A11
A0 A10
Example of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
Setting
A2/3
COL
1, 0
00 (8 bits)
Column Address
Output Cycle
A17
A16
2 2 3
A25* *
2 2
A24*
A13
1
L/H*
A11
2
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Section 12 Bus State Controller (BSC)
SDRAM Pin
A13 (BA1)
A12 (BA0)
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Rev. 4.00 Sep. 14, 2005 Page 343 of 982
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Unused
REJ09B0023-0400