Table 12.3 Address Space Map 2 (Cmncr.map = 1) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)

Table 12.3 Address Space Map 2 (CMNCR.MAP = 1)

Physical Address
H'00000000 to
H'03FFFFFF
H'04000000 to
H'07FFFFFF
H'08000000 to
H'0BFFFFFF
H'0C000000 to
H'0FFFFFFF
H'10000000 to
H'13FFFFFF
H'14000000 to
H'17FFFFFF
H'18000000 to
H'1BFFFFFF
H'1C000000 to
H'1FFFFFFF
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. For area 5, the CS5BBCR and CS5BWCR registers and the CS5B signal are valid.
For area 6, the CS6BBCR and CS6BWCR registers and the CS6B signal are valid.
3. Access the address indicated in section 24, List of Registers, for the on-chip I/O register
in area 1. Do not access area 1 addresses which are not described in the register map.
Otherwise, the correct operation cannot be guaranteed.
Rev. 4.00 Sep. 14, 2005 Page 276 of 982
REJ09B0023-0400
Area
Area 0
Area 1
Area 2
Area 3
Area 4
2
Area 5*
2
Area 6*
Area 7
Memory to be
Connected
Normal memory
Burst ROM
(Asynchronous)
Burst ROM
(Synchronous)
Internal I/O register
3
area*
Normal memory
Byte-selection SRAM
SDRAM
Normal memory
Byte-selection SRAM
SDRAM
Normal memory
Byte-selection SRAM
Burst ROM
(Asynchronous)
Normal memory
Byte-selection SRAM
MPX-I/O
Normal memory
Byte-selection SRAM
Burst MPX-I/O
1
Reserved*
Capacity
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes