Renesas HD6417641 Hardware Manual page 444

Section 12 Bus State Controller (BSC)
BSC Register Setting
CSnBCR CS3WCR.
Idle WTRP
Setting Setting
1 2
1 3
1 3
1 3
1 3
2 0
2 0
2 0
2 0
2 1
2 1
2 1
2 1
2 2
2 2
2 2
2 2
2 3
2 3
2 3
2 3
4 0
4 0
4 0
4 0
4 1
4 1
4 1
4 1
Rev. 4.00 Sep. 14, 2005 Page 394 of 982
REJ09B0023-0400
CS3WCR.
TRWL Read to
Setting Read
3 3/3/3/3
0 4/4/4/4
1 4/4/4/4
2 4/4/4/4
3 4/4/4/4
0 3/3/3/3
1 3/3/3/3
2 3/3/3/3
3 3/3/3/3
0 3/3/3/3
1 3/3/3/3
2 3/3/3/3
3 3/3/3/3
0 3/3/3/3
1 3/3/3/3
2 3/3/3/3
3 3/3/3/3
0 4/4/4/4
1 4/4/4/4
2 4/4/4/4
3 4/4/4/4
0 5/5/5/5
1 5/5/5/5
2 5/5/5/5
3 5/5/5/5
0 5/5/5/5
1 5/5/5/5
2 5/5/5/5
3 5/5/5/5
CPU Access
Write to Read to
Write Write
5/5/5/5 3/3/4/5
3/3/3/3 4/4/4/5
4/4/4/4 4/4/4/5
5/5/5/5 4/4/4/5
6/6/6/6 4/4/4/5
2/2/2/3 3/3/4/5
2/2/2/3 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
2/2/2/2 3/3/4/5
2/2/2/2 3/3/4/5
3/3/3/3 3/3/4/5
4/4/4/4 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
4/4/4/4 3/3/4/5
5/5/5/5 3/3/4/5
3/3/3/3 4/4/4/5
4/4/4/4 4/4/4/5
5/5/5/5 4/4/4/5
6/6/6/6 4/4/4/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
4/4/4/4 5/5/5/5
DMAC Access
Write to Read to
Read Write
5/5/5/5 3
3/3/3/3 4
4/4/4/4 4
5/5/5/5 4
6/6/6/6 4
2/2/2/2 3
2/2/2/2 3
2/2/2/2 3
3/3/3/3 3
2/2/2/2 3
2/2/2/2 3
3/3/3/3 3
4/4/4/4 3
2/2/2/2 3
3/3/3/3 3
4/4/4/4 3
5/5/5/5 3
3/3/3/3 4
4/4/4/4 4
5/5/5/5 4
6/6/6/6 4
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
4/4/4/4 5
Write to
Read
5
3
4
5
6
2
2
2
3
2
2
3
4
2
3
4
5
3
4
5
6
4
4
4
4
4
4
4
4