Figure 25.25 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, Cas Latency 2, Wtrcd = 0 Cycle, Wtrp = 1 Cycle) - Renesas HD6417641 Hardware Manual

Tr
CKIO
t
AD1
Row
A25 to A0
address
t
AD1
1
A12/A11*
t
CSD1
CSn
t
RWD1
RD/WR
t
RASD1
RASU/L
CASU/L
t
DQMD1
DQMxx
D31 to D0
BS
CKE
t
DACD
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)
Td1
TC1 TC2 Tc3
t t t
AD1 AD1 AD1
Column
address
t
AD1
Read command
t
RASD1
t
CASD1
t
RDS2
t
BSD
(High)
Section 25 Electrical Characteristics
Td2 Td3 Td4
Tc4
t
AD1
(1 to 4)
t t
AD1 AD1
ReadA
command
t
CASD1
t
t
RDS2
RDH2
t
BSD
Rev. 4.00 Sep. 14, 2005 Page 937 of 982
Tde
t
AD1
t
CSD1
t
RWD1
t
DQMD1
t
RDH2
t
DACD
REJ09B0023-0400