Figure 25.32 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: Read Command, Same Row Address, Cas Latency 2, Wtrcd = 0 Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11*
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
CKE
DACKn*
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 944 of 982
REJ09B0023-0400
Tc1 Tc2
t t
AD1 AD1
Column
address
t
AD1
1
Read command
t
CSD1
t
RWD1
t
RASD1
t
CASD1
t
DQMD1
t
BSD
t
DACD
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Td1 Td2 Td3
Tc3 Tc4
t
AD1
t
CASD1
t t
RDS2 RDH2
t
BSD
(High)
Td4
Tde
t
AD1
t
CSD1
t
RWD1
t
DQMD1
t t
RDS2 RDH2
t
DACD