Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Rev.4.00 Revision Date: Sep. 14, 2005 Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series SH7641 Hardware Manual SH7641...
Page 2 Rev. 4.00 Sep. 14, 2005 Page ii of l...
Page 3 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 4 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Robustness (Reference Values) of the LSI against Static-electricity-induced Breakdown Machine Model Method Human Body Model Method Charged Device Model Method For the details on the quality assurance of this LSI, contact your nearest Renesas Technology sales representative. ± 200 V or more ± 1500 V or more ±...
Page 6 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
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Page 8 The SH7641 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems.
Page 9 Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ SH7641manuals: Document Title SuperH RISC engine SH7641Hardware Manual SH-3/SH-3E/SH3-DSP Software Manual...
Page 10 Abbreviations Analog to digital converter Arithmetic logic unit bits per pixel bits per second Bus state controller CODEC Coder-decoder Clock pulse generator Central processing unit Cyclic redundancy check DMAC Direct memory access controller Digital signal processor Electrostatic discharge Error checking and correction Elementary time unit FIFO First-in first-out...
Page 11 Universal serial bus Watch dog timer Rev. 4.00 Sep. 14, 2005 Page xi of l...
Page 12 Rev. 4.00 Sep. 14, 2005 Page xii of l...
Page 13: Table Of Contents
Section 1 Overview...1 Features... 1 Block Diagram ... 7 Pin Assignments... 8 Pin functions ... 9 Section 2 CPU...25 Registers... 25 2.1.1 General Registers... 29 2.1.2 Control Registers ... 31 2.1.3 System Registers... 35 2.1.4 DSP Registers ... 35 Data Formats... 42 2.2.1 Register Data Format (Non-DSP Type)...
Page 14 3.1.5 Shift Operations ... 109 3.1.6 Most Significant Bit Detection Operation ... 112 3.1.7 Rounding Operation... 115 3.1.8 Overflow Protection... 117 3.1.9 Data Transfer Operation ... 118 3.1.10 Local Data Move Instruction ... 122 3.1.11 Operand Conflict ... 123 DSP Addressing... 124 3.2.1 DSP Repeat Control...
Page 15 Register Descriptions ... 166 6.2.1 Standby Control Register (STBCR)... 166 6.2.2 Standby Control Register 2 (STBCR2)... 167 6.2.3 Standby Control Register 3 (STBCR3)... 168 6.2.4 Standby Control Register 4 (STBCR4)... 170 Operation ... 171 6.3.1 Sleep Mode ... 171 6.3.2 Standby Mode ...
Page 16 9.1.1 TRAPA Exception Register (TRA) ... 198 9.1.2 Exception Event Register (EXPEVT)... 199 9.1.3 Interrupt Event Register 2 (INTEVT2)... 199 Exception Handling Function ... 200 9.2.1 Exception Handling Flow ... 200 9.2.2 Exception Vector Addresses... 201 9.2.3 Exception Codes ... 201 9.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ...
Page 17 10.6.2 Timing to Clear an Interrupt Source ... 240 Section 11 User Break Controller (UBC) ...241 11.1 Features... 241 11.2 Register Descriptions ... 243 11.2.1 Break Address Register A (BARA) ... 243 11.2.2 Break Address Mask Register A (BAMRA)... 244 11.2.3 Break Bus Cycle Register A (BBRA)...
Page 18 12.4.4 SDRAM Control Register (SDCR)... 314 12.4.5 Refresh Timer Control/Status Register (RTCSR)... 317 12.4.6 Refresh Timer Counter (RTCNT)... 319 12.4.7 Refresh Time Constant Register (RTCOR) ... 319 12.4.8 Reset Wait Counter (RWTCNT) ... 320 12.5 Operating Description... 321 12.5.1 Endian/Access Size and Data Alignment... 321 12.5.2 Normal Space Interface ...
Page 19 Section 14 U Memory...451 14.1 Features... 451 14.2 U Memory Access from CPU ... 452 14.3 U Memory Access from DSP... 452 14.4 U Memory Access from DMAC ... 452 14.5 Usage Note... 453 14.6 Sleep Mode ... 453 14.7 Address Error ... 453 Section 15 User Debugging Interface (H-UDI) ...455 15.1 Features...
Page 20 16.3.9 I C Bus Shift Register (ICDRS)... 487 16.3.10 NF2CYC Register (NF2CYC)... 487 16.4 Operation ... 488 16.4.1 I C Bus Format... 488 16.4.2 Master Transmit Operation... 489 16.4.3 Master Receive Operation ... 491 16.4.4 Slave Transmit Operation ... 493 16.4.5 Slave Receive Operation...
Page 21 18.3.7 Timer General Register (TGR) ... 553 18.3.8 Timer Start Register (TSTR) ... 554 18.3.9 Timer Synchro Register (TSYR) ... 554 18.3.10 Timer Output Master Enable Register (TOER) ... 556 18.3.11 Timer Output Control Register (TOCR)... 557 18.3.12 Timer Gate Control Register (TGCR) ... 559 18.3.13 Timer Subcounter (TCNTS) ...
Page 22 18.7.13 Buffer Operation Setting in Complementary PWM Mode ... 636 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag ... 637 18.7.15 Overflow Flags in Reset Sync PWM Mode... 638 18.7.16 Conflict between Overflow/Underflow and Counter Clearing ... 638 18.7.17 Conflict between TCNT Write and Overflow/Underflow ...
Page 23 19.3.12 Line Status Register (SCLSR) ... 720 19.4 Operation ... 721 19.4.1 Overview... 721 19.4.2 Operation in Asynchronous Mode ... 723 19.4.3 Synchronous Operation... 733 19.5 SCIF Interrupts and DMAC... 742 19.6 Usage Notes ... 743 Section 20 USB Function Module ...747 20.1 Features...
Page 24 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) ... 774 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) ... 776 20.4.6 EP3 Interrupt-IN Transfer... 778 20.5 Processing of USB Standard Commands and Class/Vendor Commands ... 779 20.5.1 Processing of Commands Transmitted by Control Transfer... 779 20.6 Stall Operations...
Page 25 21.3.6 Input Sampling and A/D Conversion Time ... 810 21.4 Interrupt and DMAC Transfer Request... 812 21.5 Definitions of A/D Conversion Accuracy... 813 21.6 Usage Notes ... 815 21.6.1 Setting Analog Input Voltage ... 815 21.6.2 Processing of Analog Input Pins... 815 21.6.3 Permissible Signal Source Impedance ...
Page 26 23.4.2 Port D Data Register (PDDR)... 850 23.5 Port E ... 851 23.5.1 Register Description ... 852 23.5.2 Port E Data Register (PEDR)... 852 23.6 Port F ... 853 23.6.1 Register Description ... 854 23.6.2 Port F Data Register (PFDR) ... 854 23.7 Port G...
Page 27 25.3.12 H-UDI Related Pin Timing... 960 25.3.13 USB Module Signal Timing ... 962 25.3.14 USB Transceiver Timing ... 963 25.3.15 AC Characteristics Measurement Conditions ... 964 25.4 A/D Converter Characteristics ... 965 Appendix ...967 Pin States... 967 When Other Function is Selected... 967 When I/O Port is Selected...
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Page 29 Figures Section 1 Overview Figure 1.1 Block Diagram ... 7 Figure 1.2 Pin Assignments (BGA-256)... 8 Section 2 CPU Figure 2.1 Register Configuration in Each Processing Mode (1) ... 27 Figure 2.2 Register Configuration in Each Processing Mode (2) ... 28 Figure 2.3 General Registers (Not in DSP Mode) ...
Page 30 Figure 3.14 Data Transfer Operation Flow... 119 Figure 3.15 Single Data-Transfer Operation Flow (Word)... 120 Figure 3.16 Single Data-Transfer Operation Flow (Longword) ... 121 Figure 3.17 Local Data Move Instruction Flow... 122 Figure 3.18 Restriction of Interrupt Acceptance in Repeat Loop ... 128 Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.W...
Page 31 Section 11 User Break Controller (UBC) Figure 11.1 Block Diagram of User Break Controller... 242 Section 12 Bus State Controller (BSC) Figure 12.1 BSC Functional Block Diagram... 271 Figure 12.2 Address Space ... 274 Figure 12.3 Normal Space Basic Access Timing (Access Wait 0)... 324 Figure 12.4 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0) ...
Page 32 Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) ... 364 Figure 12.29 Auto-Refresh Timing ... 366 Figure 12.30 Self-Refresh Timing ... 367 Figure 12.31 Low-Frequency Mode Access Timing ... 369 Figure 12.32 Power-Down Mode Access Timing ... 370 Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC)...
Page 33 Figure 13.8 Example of DMA Transfer Timing in Single Address Mode... 436 Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)... 437 Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection)...
Page 34 Figure 16.9 Slave Transmit Mode Operation Timing (1) ... 494 Figure 16.10 Slave Transmit Mode Operation Timing (2) ... 495 Figure 16.11 Slave Receive Mode Operation Timing (1)... 496 Figure 16.12 Slave Receive Mode Operation Timing (2)... 497 Figure 16.13 Clocked Synchronous Serial Transfer Format... 497 Figure 16.14 Transmit Mode Operation Timing...
Page 35 Figure 18.20 Example of PWM Mode Setting Procedure ... 578 Figure 18.21 Example of PWM Mode Operation (1) ... 578 Figure 18.22 Example of PWM Mode Operation (2) ... 579 Figure 18.23 Example of PWM Mode Operation (3) ... 580 Figure 18.24 Example of Phase Counting Mode Setting Procedure...
Page 36 Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) ... 615 Figure 18.54 Count Timing in Internal Clock Operation... 619 Figure 18.55 Count Timing in External Clock Operation ... 619 Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode)... 620 Figure 18.57 Output Compare Output Timing (Normal Mode/PWM Mode)...
Page 37 Figure 18.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode... 649 Figure 18.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode... 650 Figure 18.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 ... 651 Figure 18.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 ...
Page 38 Figure 18.117 Output-Level Detection Operation ... 682 Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.1 Block Diagram of SCIF... 687 Figure 19.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ... 723 Figure 19.3 Sample Flowchart for SCIF Initialization ...
Page 39 Figure 20.16 EP2 PKTE Operation ... 785 Figure 20.17 Example of USB Function Module External Circuitry (For On-Chip Transceiver)... 787 Figure 20.18 Example of USB Function Module External Circuitry (For External Transceiver) ... 788 Figure 20.19 IRQ0 and IRQ1 Interrupt Circuitry ... 790 Figure 20.20 USB Standby Operation Timing ...
Page 40 Section 25 Electrical Characteristics Figure 25.1 Power-On Sequence ... 908 Figure 25.2 EXTAL Clock Input Timing ... 917 Figure 25.3 CKIO Clock Input Timing ... 917 Figure 25.4 CKIO and CKIO2 Clock Input Timing ... 917 Figure 25.5 Oscillation Settling Timing (Power-On) ... 918 Figure 25.6 Phase Difference between CKIO and CKIO2 ...
Page 41 Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) ... 939 Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) ... 940 Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) ...
Page 42 Figure 25.48 MTU Clock Input Timing ... 956 Figure 25.49 POE Input/Output Timing ... 957 Figure 25.50 I C Bus Interface Input/Output Timing ... 959 Figure 25.51 TCK Input Timing... 960 Figure 25.52 TRST Input Timing (Reset-Hold State) ... 961 Figure 25.53 H-UDI Data Transfer Timing...
Page 43 Section 1 Overview Table 1.1 Features... 1 Table 1.2 Pin functions ... 9 Table 1.3 Pin Functions ... 18 Section 2 CPU Table 2.1 Initial Register Values... 28 Table 2.2 Destination Register in DSP Instructions... 37 Table 2.3 Source Register in DSP Operations ... 38 Table 2.4 DSR Register Bits...
Page 44 Table 2.31 DSP Operation Instructions ... 90 Table 2.32 DC Bit Update Definitions ... 96 Table 2.33 Examples of NOPX and NOPY Instruction Codes... 98 Section 3 DSP Operation Table 3.1 Variation of ALU Fixed-Point Operations... 100 Table 3.2 Correspondence between Operands and Registers ... 100 Table 3.3 Variation of ALU Integer Operations ...
Page 45 Table 7.8 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1)... 186 Section 8 X/Y Memory Table 8.1 X/Y Memory Specifications ... 193 Section 9 Exception Handling Table 9.1 Exception Event Vectors... 204 Table 9.2 Type of Reset... 206 Table 9.3 Instruction Positions and Restriction Types...
Page 46 Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (3)... 344 Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1... 345 Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-2... 346 Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-1...
Page 47 Section 14 U Memory Table 14.1 U Memory Specifications ... 451 Section 15 User Debugging Interface (H-UDI) Table 15.1 Pin Configuration... 456 Table 15.2 H-UDI Commands... 458 Table 15.3 This LSI Pins and Boundary Scan Register Bits... 459 Table 15.4 Reset Configuration ...
Page 48 Table 18.27 Output Level Select Function ... 558 Table 18.28 Output level Select Function... 560 Table 18.29 Register Combinations in Buffer Operation ... 571 Table 18.30 Cascaded Combinations... 574 Table 18.31 PWM Output Registers and Output Pins ... 577 Table 18.32 Phase Counting Mode Clock Input Pins ...
Page 49 Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode) ... 811 Table 21.5 Interrupt and DMAC Transfer Request ... 812 Section 22 Pin Function Controller (PFC) Table 22.1 List of Multiplexed Pins... 819 Section 23 I/O Ports Table 23.1 Port A Data Register (PADR) Read/Write Operations ...
Page 50 Appendix Table A.1 Pin States in Reset State, Power Down Mode, and Bus-Released States When Other Function is Selected... 967 Table A.2 Pin States in Reset State, Power Down Mode, and Bus-Released States When I/O Port is Selected... 971 Rev. 4.00 Sep. 14, 2005 Page l of l...
Page 51: Section 1 Overview
This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original 32- bit SuperH RISC engine architecture CPU with a digital signal processing (DSP) extension as its core, with 16-kbyte of cache memory, 16-kbyte of an on-chip X/Y memory, and peripheral functions required for system configuration such as an interrupt controller.
Page 52: Section 1 Overview
Section 1 Overview Items Specification • Mixture of 16-bit and 32-bit instructions • 32-/40-bit internal data paths • Multiplier, ALU, barrel shifter and DSP register • Large DSP data registers  Six 32-bit data registers  Two 40-bit data registers •...
Page 53: Section 1 Overview
Items Specification • Cache memory 16-kbyte cache, mixed instruction/data • 256 entries, 4-way set associative, 16-byte block length • Write-back, write-through, LRU replacement algorithm • 1-stage write-back buffer • Maximum 2 ways of the cache can be locked • X/Y memory Three independent read/write ports ...
Page 54 Section 1 Overview Items Specification • Bus state controller Physical address space divided into eight areas, four areas (area 0, (BSC) areas 2 to 4), each a maximum of 64 Mbytes and other four areas (areas 5A, 5B, areas 6A, 6B), each a maximum of 32 Mbytes •...
Page 55 Items Specification • Advanced user Six output pins debugger (AUD) • Trace of branch source/destination address • Window data trace function • Full trace function  All trace data can be output by stalling the CPU even when the • Real-time trace function ...
Page 56 Section 1 Overview Items Specification • 16-bit counter × 2 channels Compare match timer (CMT) • Selection of four clocks • Interrupt request or DMA transfer request can be generated by compare-match • Serial communication 3 channels interface with FIFO •...
Page 57: Block Diagram
Block Diagram The block diagram of this LSI is shown in figure1.1. Memory U Memory CACHE External Bus Interface [Legend] ADC: A/D converter AUD: Advanced user debugger BSC: Bus state controller CACHE: Cache memory CMT: Compare match timer CPG/WDT: Clock Pulse generator/Watch dog Timer CPU: Central processing unit DMAC:...
Page 58: Pin Assignments
Section 1 Overview Pin Assignments The pin assignments of this LSI is shown in figure 1.2. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.2 Pin Assignments (BGA-256) Rev.
Page 59: Pin Functions
Pin functions Table 1.2 summarizes the pin functions. Table 1.2 Pin functions (BGA256) Pin Name VssQ VccQ CS3/PTA[3] CS2/PTA[2] UCLK/PTB[0] VBUS/PTB[1] SUSPND/PTB[2] XVDATA/PTB[3] TXENL/PTB[4] VccQ VssQ TXDMNS/PTB[5] TXDPLS/PTB[6] DMNS/PTB[7] Description Data bus Data bus Data bus Data bus Data bus Data bus Ground for I/O circuits (0V) Data bus...
Page 60 Section 1 Overview (BGA256) Pin Name DPLS/PTB[8] A19/PTA[8] A20/PTA[9] A21/PTA[10] A22/PTA[11] A23/PTA[12] A24/PTA[13] VssQ AUDCK VccQ A25/PTA[14] AUDATA[0]/PTJ[8] AUDATA[1]/PTJ[9] AUDATA[2]/PTJ[10] AUDATA[3]/PTJ[11] AUDSYNC/PTJ[12] TRST IRQ0/PTJ[0] IRQ1/PTJ[1] VssQ IRQ2/PTJ[2] Rev. 4.00 Sep. 14, 2005 Page 10 of 828 REJ09B0023-0400 Description USB D+ input from Receiver/Port B Ground (0V) Address bus Power supply (1.8V)
Page 61 (BGA256) Pin Name VccQ IRQ3/PTJ[3] IRQ4/PTJ[4] IRQ5/PTJ[5] IRQ6/PTJ[6] IRQ7/PTJ[7] SCK0/PTH[0] CTS0/PTH[1] TxD0/PTH[2] RxD0/PTH[3] RTS0/PTH[4] SCK1/PTH[5] CTS1/PTH[6] TxD1/PTH[7] RxD1/PTH[8] RTS1/PTH[9] SCK2/PTH[10] CTS2/PTH[11] TxD2/PTH[12] RxD2/PTH[13] VccQ RTS2/PTH[14] VssQ TIOC4D/PTE[0] TIOC4C/PTE[1] TIOC4B/PTE[2] TIOC4A/PTE[3] TIOC3D/PTE[4] TIOC3B/PTE[6] Description Power supply for I/O circuits (3.3V) External interrupt request/Port J External interrupt request/Port J External interrupt request/Port J External interrupt request/Port J...
Page 62 Section 1 Overview (BGA256) Pin Name TIOC3C/PTE[5] TIOC3A/PTE[7] TIOC2B/PTE[8] TIOC2A/PTE[9] TIOC1B/PTE[10] TIOC1A/PTE[11] TIOC0D/PTE[12] TIOC0C/PTE[13] TIOC0B/PTE[14] TIOC0A/PTE[15] VssQ TCLKD/PTF[8] VccQ TCLKC/PTF[9] TCLKB/PTF[10] TCLKA/PTF[11] POE0/PTF[12] POE1/PTF[13] POE2/PTF[14] POE3/PTF[15] PTF[0] PTF[1] PTF[2] PTF[3] PTF[4] PTF[5] PTF[6] Rev. 4.00 Sep. 14, 2005 Page 12 of 828 REJ09B0023-0400 Description Timer input output 3C/Port E...
Page 63 (BGA256) Pin Name VssQ PTF[7] VccQ PTG[8] SCL/PTG[9] SDA/PTG[10] PTG[11] PTG[12] PTG[13] AVss (AD) AN[0]/PTG[0] AN[1]/PTG[1] AN[2]/PTG[2] AN[3]/PTG[3] AN[4]/PTG[4] AN[5]/PTG[5] AN[6]/PTG[6] AVcc (AD) AN[7]/PTG[7] VccQ* DREQ0/PTC[9] DREQ1/PTC[10] STATUS0/PTC[14] STATUS1/PTC[15] BREQ/PTC[6] BACK/PTC[7] VccQ* VccQ* ASEBRKAK/PTC[13] Description Ground for I/O circuits (0V) Port F Power supply for I/O circuits (3.3V) Port G...
Page 64 Section 1 Overview (BGA256) Pin Name RESETP VccQ VssQ XTAL EXTAL RESETM ASEMD0 Vss(PLL2) Vcc(PLL2) Vcc(PLL1) Vss(PLL1) VccQ* CS6B/PTC[4] VssQ CS6A/PTC[3] VccQ CS5B/PTC[2] CS5A/PTC[1] CS4/PTC[0] WAIT TEND/PTC[8] FRAME/PTC[5] Rev. 4.00 Sep. 14, 2005 Page 14 of 828 REJ09B0023-0400 Description Power−on Reset request Power supply for I/O circuits (3.3V) Ground for I/O circuits (0V) Clock oscillator pin...
Page 65 (BGA256) Pin Name DACK0/PTC[11] VssQ DACK1/PTC[12] VccQ D31/PTD[15] D30/PTD[14] D29/PTD[13] D28/PTD[12] D27/PTD[11] D26/PTD[10] D25/PTD[9] D24/PTD[8] D23/PTD[7] D22/PTD[6] D21/PTD[5] D20/PTD[4] VssQ D19/PTD[3] VccQ D18/PTD[2] D17/PTD[1] D16/PTD[0] CKIO2 VccQ CKIO VssQ RD/WR VccQ Description DMA request acknowledge/Port C Ground (0V) Ground for I/O circuits (0V) DMA request acknowledge/Port C Power supply for I/O circuits (3.3V) Data bus/Port D...
Page 66 Section 1 Overview (BGA256) Pin Name WE0/DQMLL VssQ WE1/DQMLU CASU/PTA[5] WE3/DQMUU/AH RASU/PTA[7] WE2/DQMUL CKE/PTA[1] CASL/PTA[4] RASL/PTA[6] VssQ VccQ Rev. 4.00 Sep. 14, 2005 Page 16 of 828 REJ09B0023-0400 Description D7 to D0 Select signal/DQM (SDRAM) Ground for I/O circuits (0V) D15 to D8 Select signal/DQM (SDRAM) CAS for Upper-32M-byte address/Port A D31 to D24 Select signal/DQM (SDRAM)/...
Page 67 (BGA256) Pin Name A0/PTA[0] VssQ VccQ Notes: Treatment of unused pins: All the I/O buffers except PTG10, PTG9, and PTG 7 to PTG 0 (IIC2 and analog pins) have weak keepers. Weak-keeper circuits are provided on input/output pins, and fix the pin inputs to high or low level when the pins are not driven externally.
Page 68 Section 1 Overview Table 1.3 lists the pin functions. Table 1.3 Pin Functions Classification Symbol Power supply VccQ VssQ Clock Vcc (PLL1) Vss (PLL1) Vcc (PLL2) Vcc (PLL2) EXTAL XTAL Rev. 4.00 Sep. 14, 2005 Page 18 of 828 REJ09B0023-0400 Name Function Power supply...
Page 69 Classification Symbol Clock CKIO CKIO2 Operating mode MD3, MD2, control RESETP System control RESETM STATUS1, STATUS0 BREQ BACK Interrupts IRQ7 to IRQ0 I Address bus A25 to A0 Data bus D31 to D0 CS0, Bus control CS2 to CS4, CS5A, CS5B, CS6A, CS6B Name Function...
Page 70 Section 1 Overview Classification Symbol Bus control RD/WR WE3/DQMUU/ WE2/DQMUL WE1/DQMLU WE0/DQMLL RASU, RASL CASU, CASL FRAME WAIT Rev. 4.00 Sep. 14, 2005 Page 20 of 828 REJ09B0023-0400 Name Function Read/write Read/write signal Bus start Bus-cycle start Byte specification Indicates that bits 31 to 24 of the data in the external memory or device are being written.
Page 71 Classification Symbol DREQ0, Direct memory DREQ1 access controller (DMAC) DACK0, DACK1 TEND0 User debugging interface (H-UDI) TRST Advanced user AUDATA3 to debugger AUDATA0 (AUD) AUDCK AUDSYNC ASEBRKAK E10A interface ASEMD0 C bus interface 2 Name Function DMA-transfer Input pin for external requests for request DMA transfer.
Page 72 Section 1 Overview Classification Symbol Multi function timer- TCLKA pulse unit (MTU) TCLKB TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D POE3 to Port output enable POE0 (POE) Serial SCK0 communication SCK1 interface with FIFO...
Page 73 Classification Symbol USB function XVDATA module DPLS DMNS TXDPLS TXDMNS TXENL VBUS SUSPND UCLK A/D converter AN7 to AN0 AVcc AVss Name Function Data input Input pin for receive data from USB differential receiver D+ input Input pin for D+ signal from USB receiver D- input Input pin for D- signal from USB...
Page 74 Section 1 Overview Classification Symbol I/O ports PTA14 to PTA0 PTB8 to PTB0 PTC15 to PTC0 PTD15 to PTD0 PTE15 to PTE0 PTF15 to PTF0 PTG13 to PTG8 PTG7 to PTG0 PTH14 to PTG0 PTJ12 to PTG0 Rev. 4.00 Sep. 14, 2005 Page 24 of 828 REJ09B0023-0400 Name Function...
Page 75: Section 2 Cpu
Section 2 CPU Section 2 CPU Registers This LSI has the same registers as the SH-3. In addition, this LSI also supports the same DSP- related registers as in the SH-DSP. The basic software-accessible registers are divided into four distinct groups: •...
Page 76 Section 2 CPU The system registers are accessed by the LDS/STS instructions (the PC is software-accessible, but is included here because its contents are saved in, and restored from, SPC in exception handling). The system registers are: • MACH: Multiply and accumulate high register •...
Page 77: Figure 2.1 Register Configuration In Each Processing Mode (1)
R0_BANK1* R1_BANK1* R2_BANK1* R3_BANK1* R4_BANK1* R5_BANK1* R6_BANK1* R7_BANK1* MACH MACL R0_BANK0* R1_BANK0* R2_BANK0* R3_BANK0* R4_BANK0* R5_BANK0* R6_BANK0* R7_BANK0* (a) Register configuration for DSP mode and non_DSP mode (RB = 1) Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode.
Page 78: Figure 2.2 Register Configuration In Each Processing Mode (2)
Section 2 CPU Figure 2.2 Register Configuration in Each Processing Mode (2) Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers General registers R0 to R15 Control registers GBR, SSR, SPC RS, RE System registers MACH, MACL, PR DSP registers...
Page 79: General Registers
2.1.1 General Registers There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is used as an index register. With a number of instructions, R0 is the only register that can be used.
Page 80: Figure 2.4 General Registers (Dsp Mode)
Section 2 CPU On the other hand, registers R2 to R9 are also used for DSP data address calculation when DSP extension is enabled (see figure 2.4). Other symbols that represent the purpose of the registers in DSP type instructions is shown in [ ]. R2 [As] R3 [As] R4 [As, Ax]...
Page 81: Control Registers
Ay1: .REG (R7) .REG (R9) As0: .REG (R4) As1: .REG (R5) As2: .REG (R2) As3: .REG (R3) .REG (R8) 2.1.2 Control Registers This LSI has 8 control registers: SR, SSR, SPC, GBR, VBR, RS, RE, and MOD (figure 2.5). SSR, SPC, GBR and VBR are the same as the SH-3 registers.
Page 82 Section 2 CPU and end addresses of a loop (the contents of the RS and RE registers are slightly different from the actual loop start and end addresses). The modulo register, MOD, is provided to implement modulo addressing for circular data buffering.
Page 83: Figure 2.5 Control Registers (1)
28 27 16 15 13 12 DSP DMY DMX M RB bit: Register bank bit; used to define the general registers. RB = 1: R0_BANK1 to R7_BANK1 are used as general registers. R0_BANK0 to R7_BANK0 accessed by LDC/STC instructions. RB = 0: R0_BANK0 to R7_BANK0 are used as general registers.
Page 84: Figure 2.5 Control Registers (2)
Section 2 CPU ME: Modulo end address, MS: Modulo start address Saved status register (SSR) Stores current SR value at time of exception to indicate processor status when returning to instruction stream from exception handler. Saved program counter (SPC) Stores current PC value at time of exception to indicate return address on completion of exception handling. Global base register (GBR) Stores base address of GBR-indirect addressing mode.
Page 85: System Registers
2.1.3 System Registers This LSI has four system registers, MACL, MACH, PR and PC (figure 2.6). MACH MACL The DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. Therefore, instructions for data transfer between general registers and system registers are supported for these registers.
Page 86 Section 2 CPU When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but no other registers can be stored.
Page 87: Table 2.2 Destination Register In Dsp Instructions
Table 2.2 Destination Register in DSP Instructions Registers Instructions A0, A1 Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data MOVS.W transfer MOVS.L A0G, A1G Data MOVS.W transfer MOVS.L X0, X1 Fixed-point, PSHA, Y0, Y1 PMULS M0, M1 Integer, logical, PDMSB, PSHL Data MOVX/Y.W, MOVS.W transfer...
Page 88: Table 2.3 Source Register In Dsp Operations
Section 2 CPU Table 2.3 Source Register in DSP Operations Registers Instructions A0, A1 Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data MOVX/Y.W, MOVS.W transfer MOVS.L A0G, A1G Data MOVS.W transfer MOVS.L X0, X1 Fixed-point, PDMSB, Y0, Y1 PSHA M0, M1 Integer Logical, PSHL, PMULS Data...
Page 89: Figure 2.7 Dsp Registers
(a) DSP Data Registers (b) DSP Status Register (DSR) Reset status DSR: All zeros Others: Undefined Figure 2.7 DSP Registers 16 bits 16 bits 8 bits MOVX.W MOVS.W, MOVS.L Figure 2.8 Connections of DSP Registers and Buses CS [2:0] 32 bits MOVY.W MOVS.W, MOVS.L...
Page 90 Section 2 CPU The DSP unit has one control register, the DSP status register (DSR). DSR holds the status of DSP data operation results (zero, negative, and so on) and has a DC bit which is similar to the T bit in the CPU.
Page 91: Table 2.4 Dsr Register Bits
Table 2.4 DSR Register Bits Bits Name (Abbreviation) 31 to 8 Reserved bits Signed Greater Than bit (GT) Zero bit (Z) Negative bit (N) Overflow bit (V) 3 to 1 Condition Select bits (CS) DSP Condition bit (DC) Note: After execution of a PADDC/PSUBC instruction, the DC bit sets the status of the operation result in carry/borrow mode regardless of the CS bits.
Page 92: Data Formats
Section 2 CPU DSR is assigned as a system register and the following load/store instructions are provided: STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; When DSR is read by an STS instruction, the upper bits (bits 31 to 8) are all 0. Data Formats 2.2.1 Register Data Format (Non-DSP Type)
Page 93: Figure 2.10 Data Formats
DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer With guard bits Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) DSP type logical CPU type integer Longword S: Sign bit : Binary point The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent...
Page 94: Memory Data Formats
Section 2 CPU 2.2.3 Memory Data Formats Memory data formats are classified into byte, word, and longword. Byte data can be accessed from any address, but an address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed.
Page 95: Table 2.5 Word Data Sign Extension
Table 2.5 Word Data Sign Extension This LSI's CPU MOV.W @(disp,PC),R1 R1,R0 .DATA.W H'1234 Note: Immediate data is referenced by @(disp,PC). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly on memory.
Page 96: Table 2.7 T Bit
Section 2 CPU Table 2.7 T Bit This LSI's CPU Description If R0 ≥ R1, the T bit is set. CMP/GE R1,R0 TRGET0 A branch is made to TRGET0 if R0 ≥ R1, or to TRGET1 if R0 < R1. TRGET1 #–1,R0 The T bit is not set by ADD.
Page 97: Table 2.9 Absolute Address Referencing
Table 2.9 Absolute Address Referencing Type This LSI's CPU Absolute address MOV.L MOV.B .DATA.L 16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode.
Page 98: Instruction Formats
Section 2 CPU Instruction Formats 2.4.1 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions Addressing Instruction Mode Format Register direct...
Page 99 Addressing Instruction Mode Format Register @(disp:4, Rn) indirect with displacement Indexed @(R0, Rn) register indirect @(disp:8, GBR) Effective address is register GBR contents indirect with displacement Indexed GBR @(R0, GBR) indirect Effective Address Calculation Method Effective address is register Rn contents with 4-bit displacement disp added.
Page 100 Section 2 CPU Addressing Instruction Mode Format PC-relative with @(disp:8, PC) displacement PC-relative disp:8 disp:12 Rev. 4.00 Sep. 14, 2005 Page 50 of 982 REJ09B0023-0400 Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added. After disp is zero- extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size.
Page 101: Dsp Data Addressing
Addressing Instruction Mode Format Immediate #imm:8 #imm:8 #imm:8 2.4.2 DSP Data Addressing Two different memory accesses are made with DSP instructions. The two kinds of instructions are X and Y data transfer instructions (MOVX.W and MOVY.W) and single data transfer instructions (MOVS.W and MOVSL).
Page 102 Section 2 CPU X/Y Data Addressing: With DSP instructions, the X and Y data memory can be accessed simultaneously using the MOVX.W and MOVY.W instructions. Two address pointers are provided for DSP instructions to enable simultaneous access to X and Y data memory. Only pointer addressing can be used with DSP instructions;...
Page 103: Figure 2.12 X And Y Data Transfer Addressing
R8[Ix] +2 (INC) +0 (no update) [Legend] AU: Adder provided for DSP addressing Note: Three address processing methods: 1. Increment 2. Index register addition (Ix/Iy) 3. No increment Post-updating is used in all cases. The address pointer can be decremented by setting in the index register. Figure 2.12 X and Y Data Transfer Addressing Single Data Addressing: DSP instructions include two single data transfer instructions (MOVS.W and MOVS.L) that load data into, or store data from, a DSP register.
Page 104: Figure 2.13 Single Data Transfer Addressing
Section 2 CPU The R8 register is the index register (Is) for the address pointer (As). Single data transfer addressing is shown in figure 2.13. –2/–4 (DEC) +2/+4 (INC) +0 (no update) Note: Four address processing methods: 1. No update 2.
Page 105: Figure 2.14 Modulo Addressing
MOV.L ModAddr,Rn; LDC Rn,MOD; ModAddr: .DATA.W .DATA.W ModStart: .DATA ModEnd: .DATA The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the address register contents before update are compared with ME* in the address register as the updated value* specified for the X/Y data transfer instruction, the address pointer will not return to modulo start...
Page 106 Section 2 CPU An example of modulo addressing is given below. MS = H'7000; ME=H'7004; R4=H'A50070008; (Modulo addressing setting for address register Ax) DMX = 1; DMY = 0: As a result of the above settings, the R4 register changes as follows. ;...
Page 107 DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX), including modulo addressing, are shown below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be used have not been updated */ /* Ax is one of R4,5 */ if ( DMX==0 || DMX==1 &&...
Page 108: Cpu Instruction Formats
Section 2 CPU 2.4.3 CPU Instruction Formats Table 2.13 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register...
Page 109 Instruction Format nm type xxxx nnnn mmmm xxxx md type xxxx xxxx dddd mmmm nd4 type xxxx xxxx nnnn dddd nmd type xxxx nnnn dddd mmmm Note: In multiply-and-accumulate instructions, nnnn is the source register. Source Destination Operand Operand mmmm: register nnnn: register direct direct...
Page 110 Section 2 CPU Instruction Format d type xxxx xxxx dddd dddd d12 type xxxx dddd dddd dddd nd8 type xxxx nnnn dddd dddd i type xxxx xxxx i i i i i i i i ni type xxxx nnnn i i i i i i i i Rev.
Page 111: Dsp Instruction Formats
2.4.4 DSP Instruction Formats This LSI includes new instructions for digital signal processing. The new instructions are of the following two kinds. 1. Memory and DSP register double and single data transfer instructions (16-bit length) 2. Parallel processing instructions processed by the DSP unit (32-bit length) The instruction formats are shown in figure 2.15.
Page 112: Table 2.14 Double Data Transfer Instruction Formats
Section 2 CPU Double and Single Data Transfer Instructions: The format of double data transfer instructions is shown in table 2.14, and that of single data transfer instructions in table 2.15. Table 2.14 Double Data Transfer Instruction Formats Type Mnemonic X memory NOPX data MOVX.W @Ax,Dx...
Page 113: Table 2.15 Single Data Transfer Instruction Formats
Table 2.15 Single Data Transfer Instruction Formats Type Mnemonic Single MOVS.W @-As,Ds data MOVS.W @As,Ds transfer MOVS.W @As+,Ds MOVS.W @As+Ix,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Ix MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Ix,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Ix Note:...
Page 114: Table 2.16 A-Field Parallel Data Transfer Instructions
Section 2 CPU Table 2.16 A-Field Parallel Data Transfer Instructions Rev. 4.00 Sep. 14, 2005 Page 64 of 982 REJ09B0023-0400...
Page 115: Table 2.17 B-Field Alu Operation Instructions And Multiply Instructions (1)
Section 2 CPU Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (1) Rev. 4.00 Sep. 14, 2005 Page 65 of 982 REJ09B0023-0400...
Page 116: Table 2.17 B-Field Alu Operation Instructions And Multiply Instructions (2)
Section 2 CPU Table 2.17 B-Field ALU Operation Instructions and Multiply Instructions (2) Rev. 4.00 Sep. 14, 2005 Page 66 of 982 REJ09B0023-0400...
Page 117: Instruction Set
Instruction Set 2.5.1 CPU Instruction Set The SH-1/SH-2/SH-3 compatible instruction set consists of 67 basic instruction types divided into seven functional groups, as shown in table 2.18. Tables 2.19 to 2.24 show the instruction notation, machine code, execution time, and function. Table 2.18 CPU Instruction Types Kinds of Type...
Page 118 Section 2 CPU Kinds of Type Instruction Arithmetic operation instructions Logic operation instructions Shift instructions Rev. 4.00 Sep. 14, 2005 Page 68 of 982 REJ09B0023-0400 Op Code Function Double-precision multiplication (32 × 32 bits) Signed multiplication (16 × 16 bits) MULS Unsigned multiplication (16 ×...
Page 119 Kinds of Type Instruction Branch instructions System control instructions Total: Op Code Function Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure...
Page 120 Section 2 CPU The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order.
Page 121: Table 2.19 Data Transfer Instructions
Data Transfer Instructions Table 2.19 Data Transfer Instructions Instruction #imm,Rn MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn)
Page 122 Section 2 CPU Instruction MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) MOV.W R0,@(disp,GBR) MOV.L R0,@(disp,GBR) MOV.B @(disp,GBR),R0 MOV.W @(disp,GBR),R0 MOV.L @(disp,GBR),R0 MOVA @(disp,PC),R0 MOVT SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev. 4.00 Sep. 14, 2005 Page 72 of 982 REJ09B0023-0400 Instruction Code Operation...
Page 123: Table 2.20 Arithmetic Operation Instructions
Arithmetic Operation Instructions Table 2.20 Arithmetic Operation Instructions Instruction Instruction Code Rm,Rn 0011nnnnmmmm1100 #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL 0100nnnn00010101 CMP/PZ 0100nnnn00010001...
Page 124 Section 2 CPU Instruction Instruction Code DMULU.L Rm,Rn 0011nnnnmmmm0101 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 Rm,Rn...
Page 125: Table 2.21 Logic Operation Instructions
Instruction Instruction Code SUBV Rm,Rn 0011nnnnmmmm1011 Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required when the operation result is read from the MAC register immediately after the instruction. 2. The normal minimum number of execution cycles is one, but three cycles are required when the operation result is read from the MAC register immediately after the MUL instruction.
Page 126: Table 2.22 Shift Instructions
Section 2 CPU Shift Instructions Table 2.22 Shift Instructions Instruction Instruction Code ROTL 0100nnnn00000100 ROTR 0100nnnn00000101 ROTCL 0100nnnn00100100 ROTCR 0100nnnn00100101 SHAD Rm,Rn 0100nnnnmmmm1100 SHAL 0100nnnn00100000 SHAR 0100nnnn00100001 SHLD Rm,Rn 0100nnnnmmmm1101 SHLL 0100nnnn00000000 SHLR 0100nnnn00000001 SHLL2 0100nnnn00001000 SHLR2 0100nnnn00001001 SHLL8 0100nnnn00011000 SHLR8 0100nnnn00011001 SHLL16...
Page 127: Table 2.23 Branch Instructions
Branch Instructions Table 2.23 Branch Instructions Instruction Instruction Code label 10001011dddddddd BF/S label 10001111dddddddd label 10001001dddddddd BT/S label 10001101dddddddd label 1010dddddddddddd BRAF 0000mmmm00100011 label 1011dddddddddddd BSRF 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Note: One state when the branch is not executed. Operation If T = 0, disp ×...
Page 128: Table 2.24 System Control Instructions
Section 2 CPU System Control Instructions Table 2.24 System Control Instructions Instruction Instruction Code CLRMAC 0000000000101000 CLRS 0000000001001000 CLRT 0000000000001000 Rm,SR 0100mmmm00001110 Rm,GBR 0100mmmm00011110 Rm,VBR 0100mmmm00101110 Rm,SSR 0100mmmm00111110 Rm,SPC 0100mmmm01001110 Rm,R0_BANK 0100mmmm10001110 Rm,R1_BANK 0100mmmm10011110 Rm,R2_BANK 0100mmmm10101110 Rm,R3_BANK 0100mmmm10111110 Rm,R4_BANK 0100mmmm11001110 Rm,R5_BANK 0100mmmm11011110 Rm,R6_BANK...
Page 129 Instruction Instruction Code LDC.L @Rm+, 0100mmmm11000111 R4_BANK LDC.L @Rm+, 0100mmmm11010111 R5_BANK LDC.L @Rm+, 0100mmmm11100111 R6_BANK LDC.L @Rm+, 0100mmmm11110111 R7_BANK Rm,MACH 0100mmmm00001010 Rm,MACL 0100mmmm00011010 Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH 0100mmmm00000110 LDS.L @Rm+,MACL 0100mmmm00010110 LDS.L @Rm+,PR 0100mmmm00100110 0000000000001001 PREF 0000mmmm10000011 0000000000101011 SETS 0000000001011000 SETT 0000000000011000 SLEEP...
Page 130 Section 2 CPU Instruction Instruction Code R7_BANK,Rn 0000nnnn11110010 STC.L SR,@–Rn 0100nnnn00000011 STC.L GBR,@–Rn 0100nnnn00010011 STC.L VBR,@–Rn 0100nnnn00100011 STC.L SSR,@–Rn 0100nnnn00110011 STC.L SPC,@–Rn 0100nnnn01000011 STC.L R0_BANK, 0100nnnn10000011 @–Rn STC.L R1_BANK, 0100nnnn10010011 @–Rn STC.L R2_BANK, 0100nnnn10100011 @–Rn STC.L R3_BANK, 0100nnnn10110011 @–Rn STC.L R4_BANK, 0100nnnn11000011 @–Rn...
Page 131: Dsp Extended-Function Instructions
DSP Extended-Function Instructions 2.6.1 Introduction The newly added instructions are classified into the following three groups: 1. Additional system control instructions for the CPU unit 2. DSP unit memory-register single and double data transfer 3. DSP unit parallel processing Group 1 instructions are provided to support loop control and data transfer between CPU core registers or memory and new control registers added to the CPU core.
Page 132: Added Cpu System Control Instructions
Section 2 CPU 2.6.2 Added CPU System Control Instructions The new instructions in this class are treated as part of the CPU core functions, and therefore all the added instructions have a 16-bit code length. All the additional instructions belong to the system control instruction group.
Page 133 Instruction Instruction Code STS.L DSR,@-Rn 0100nnnn01100010 STS.L A0,@-Rn 0100nnnn01110010 STS.L X0,@-Rn 0100nnnn10000010 STS.L X1,@-Rn 0100nnnn10010010 STS.L Y0,@-Rn 0100nnnn10100010 STS.L Y1,@-Rn 0100nnnn10110010 STC.L MOD,@-Rn 0100nnnn01010011 STC.L RS,@-Rn 0100nnnn01100011 STC.L RE,@-Rn 0100nnnn01110011 LDS.L @Rn+,DSR 0100nnnn01100110 LDS.L @Rn+,A0 0100nnnn01110110 LDS.L @Rn+,X0 0100nnnn10000110 LDS.L @Rn+,X1 0100nnnn10010110 LDS.L @Rn+,Y0 0100nnnn10100110...
Page 134: Single And Double Data Transfer For Dsp Data Instructions
Section 2 CPU 2.6.3 Single and Double Data Transfer for DSP Data Instructions The new instructions in this class are provided to reduce the program code size for DSP operations. All the new instructions in this class have a 16-bit code length. Instructions in this class are divided into two groups: single data transfer instructions and double data transfer instructions.
Page 135: Table 2.26 Double Data Transfer Instructions
Table 2.26 Double Data Transfer Instructions Instruction X memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx 111100A*D*0*11** MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix 111100A*D*1*11** Y memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy 111100*A*D*0**11 MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy 111100*A*D*1**11 Instruction Code...
Page 136: Table 2.27 Single Data Transfer Instructions
Section 2 CPU Table 2.27 Single Data Transfer Instructions Instruction Instruction Code MOVS.W @-As,Ds 111101AADDDD0000 MOVS.W @As,Ds 111101AADDDD0100 MOVS.W @As+,Ds 111101AADDDD1000 MOVS.W @As+Is,Ds 111101AADDDD1100 MOVS.W Ds,@-As* 111101AADDDD0001 MOVS.W Ds,@As* 111101AADDDD0101 MOVS.W Ds,@As+* 111101AADDDD1001 MOVS.W Ds,@As+Is* 111101AADDDD1101 MOVS.L @-As,Ds 111101AADDDD0010 MOVS.L @As,Ds 111101AADDDD0110 MOVS.L @As+,Ds 111101AADDDD1010...
Page 137: Table 2.28 Correspondence Between Dsp Data Transfer Operands And Registers
The correspondence between DSP data transfer operands and registers is shown in table 2.28. CPU core registers are used as a pointer address that indicates a memory address. Table 2.28 Correspondence between DSP Data Transfer Operands and Registers Register  registers R1 ...
Page 138: Dsp Operation Instruction Set
Section 2 CPU 2.6.4 DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field.
Page 139: Figure 2.16 Sample Parallel Instruction Program
Table 2.30 Correspondence between DSP Instruction Operands and Registers ALU/BPU Operations Register — — — — — — — — When writing parallel instructions, the B-field instruction is written first, followed by the A-field instruction. A sample parallel processing program is shown in figure 2.16. PADD A0, M0, A0 PINC X1, A1 PCMP X1, M0...
Page 140: Table 2.31 Dsp Operation Instructions
Section 2 CPU Table 2.31 DSP Operation Instructions Instruction Instruction Code PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0111eeffxxyygguu PSUB Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0110eeffxxyygguu PADD Sx,Sy,Dz 111110********** 10110001xxyyzzzz PADD Sx,Sy,Dz 111110********** 10110010xxyyzzzz PADD Sx,Sy,Dz 111110********** 10110011xxyyzzzz PSUB Sx,Sy,Dz 111110********** 10100001xxyyzzzz PSUB Sx,Sy,Dz...
Page 141 Instruction Instruction Code PSHA Sx,Sy,Dz 111110********** 10010011xxyyzzzz PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz PSHL Sx,Sy,Dz 111110********** 10000010xxyyzzzz PSHL Sx,Sy,Dz 111110********** 10000011xxyyzzzz PCOPY Sx,Dz 111110********** 11011001xx00zzzz PCOPY Sy,Dz 111110********** 1111100100yyzzzz PCOPY Sx,Dz 111110********** 11011010xx00zzzz PCOPY Sy,Dz 111110********** 1111101000yyzzzz PCOPY Sx,Dz 111110********** 11011011xx00zzzz PCOPY Sy,Dz 111110********** 1111101100yyzzzz Operation...
Page 142 Section 2 CPU Instruction Instruction Code PDMSB Sx,Dz 111110********** 10011101xx00zzzz PDMSB Sy,Dz 111110********** 1011110100yyzzzz PDMSB Sx,Dz 111110********** 10011110xx00zzzz PDMSB Sy,Dz 111110********** 1011111000yyzzzz PDMSB Sx,Dz 111110********** 10011111xx00zzzz PDMSB Sy,Dz 111110********** 1011111100yyzzzz PINC Sx,Dz 111110********** 10011001xx00zzzz PINC Sy,Dz 111110********** 1011100100yyzzzz PINC Sx,Dz 111110********** 10011010xx00zzzz PINC Sy,Dz...
Page 143 Instruction Instruction Code PNEG Sy,Dz 111110********** 1110100100yyzzzz PNEG Sx,Dz 111110********** 11001010xx00zzzz PNEG Sy,Dz 111110********** 1110101000yyzzzz PNEG Sx,Dz 111110********** 11001011xx00zzzz PNEG Sy,Dz 111110********** 1110101100yyzzzz POR Sx,Sy,Dz 111110********** 10110101xxyyzzzz POR Sx,Sy,Dz 111110********** 10110110xxyyzzzz POR Sx,Sy,Dz 111110********** 10110111xxyyzzzz PAND Sx,Sy,Dz 111110********** 10010101xxyyzzzz PAND Sx,Sy,Dz 111110********** 10010110xxyyzzzz PAND Sx,Sy,Dz...
Page 144 Section 2 CPU Instruction Instruction Code PDEC Sy,Dz 111110********** 1010100100yyzzzz PDEC Sx,Dz 111110********** 10001010xx00zzzz PDEC Sy,Dz 111110********** 1010101000yyzzzz PDEC Sx,Dz 111110********** 10001011xx00zzzz PDEC Sy,Dz 111110********** 1010101100yyzzzz PCLR Dz 111110********** 100011010000zzzz PCLR Dz 111110********** 100011100000zzzz PCLR Dz 111110********** 100011110000zzzz PSHA #imm,Dz 111110********** 00010iiiiiiizzzz PSHL #imm,Dz...
Page 145 Instruction Instruction Code PSTS MACL,Dz 111110********** 110111100000zzzz PSTS MACL,Dz 111110********** 110111110000zzzz PLDS Dz,MACH 111110********** 111011010000zzzz PLDS Dz,MACH 111110********** 111011100000zzzz PLDS Dz,MACH 111110********** 111011110000zzzz PLDS Dz,MACL 111110********** 111111010000zzzz PLDS Dz,MACL 111110********** 111111100000zzzz PLDS Dz,MACL 111110********** 111111110000zzzz PADDC Sx,Sy,Dz 111110********** 10110000xxyyzzzz PSUBC Sx,Sy,Dz 111110********** 10100000xxyyzzzz PCMP Sx,Sy 111110**********...
Page 146: Table 2.32 Dc Bit Update Definitions
Section 2 CPU Table 2.32 DC Bit Update Definitions CS [2:0] Condition Mode Carry or borrow mode Negative value mode Zero value mode Overflow mode Signed greater-than mode Signed greater-or- equal mode Reserved Reserved Rev. 4.00 Sep. 14, 2005 Page 96 of 982 REJ09B0023-0400 Description The DC bit is set if an ALU arithmetic operation generates a carry...
Page 147: Figure 2.17 Examples Of Conditional Operations And Data Transfer Instructions
Conditional Operations and Data Transfer: Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made.
Page 148: Table 2.33 Examples Of Nopx And Nopy Instruction Codes
Section 2 CPU Assignment of NOPX and NOPY Instruction Codes: When there is no data transfer instruction to be parallel-processed simultaneously with a DSP operation instruction, an NOPX or NOPY instruction can be written as the data transfer instruction, or the instruction can be omitted. The instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is omitted.
Page 149: Section 3 Dsp Operation
Section 3 DSP Operation Data Operations of DSP Unit 3.1.1 ALU Fixed-Point Operations Figure 3.1 shows the ALU arithmetic operation flow. Table 3.1 shows the variation of this type of operation and table 3.2 shows the correspondence between each operand and registers. Guard Source 1 Figure 3.1 ALU Fixed-Point Arithmetic Operation Flow...
Page 150: Table 3.1 Variation Of Alu Fixed-Point Operations
Section 3 DSP Operation Table 3.1 Variation of ALU Fixed-Point Operations Mnemonic Function PADD Addition PSUB Subtraction PADDC Addition with carry PSUBC Subtraction with borrow PCMP Comparison PCOPY Data copy PABS Absolute PNEG Negation PCLR Clear Table 3.2 Correspondence between Operands and Registers Register —...
Page 151: Figure 3.2 Operation Sequence Example
Operation Sequence Example MOVX.W @(R4, R8), X0 PADD X0, Y0, A0 MOVX.W @R4+, X0 Slot Stage MOVX MA/DSP Figure 3.2 Operation Sequence Example Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result.
Page 152: Figure 3.4 Dc Bit Generation Examples In Negative Value Mode
Section 3 DSP Operation Negative Value Mode: CS[2:0] = 001: The DC flag indicates the same state as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is a positive number, the DC bit shows 0.
Page 153 Signed Greater Than Mode: CS[2:0] = 100: The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP. So, a PCMP operation should be executed in advance when a conditional operation is executed under this condition mode.
Page 154: Alu Integer Operations
Section 3 DSP Operation 3.1.2 ALU Integer Operations Figure 3.6 shows the ALU integer arithmetic operation flow. Table 3.3 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.2. Guard Source 1 Ignored...
Page 155: Alu Logical Operations
Section 3 DSP Operation In ALU integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. The guard-bit parts are effective in integer arithmetic operations if they are supported. Others are basically the same operation as ALU fixed-point arithmetic operations.
Page 156: Figure 3.7 Alu Logical Operation Flow
Section 3 DSP Operation Soruce 1 Guard Ignored Cleared Figure 3.7 ALU Logical Operation Flow Table 3.4 Variation of ALU Logical Operations Mnemonic Function PAND Logical AND Logical OR PXOR Logical exclusive OR Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR register are basically updated in accordance with the operation result.
Page 157: Fixed-Point Multiply Operation
5. Signed Greater Than Mode: CS[2:0] = 100 The DC bit is always cleared. 6. Signed Greater Than or Equal Mode: CS[2:0] = 101 The DC bit is always cleared. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits.
Page 158: Table 3.5 Variation Of Fixed-Point Multiply Operation
Section 3 DSP Operation Table 3.5 Variation of Fixed-Point Multiply Operation Mnemonic Function PMULS Signed multiplication Table 3.6 Correspondence between Operands and Registers Register     Note: The multiply operations basically generate 32-bit operation results. So when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy bit 31 of the operation result.
Page 159: Shift Operations
3.1.5 Shift Operations Shift operations can use either register or immediate value as the shift amount operand. Other source and destination operands are specified by the register. There are two kinds of shift operations. Table 3.7 shows the variation of this type of operation. The correspondence between each operand and registers, except for immediate operands, is the same as the ALU fixed-point operations as shown in table 3.2.
Page 160 Section 3 DSP Operation In this arithmetic shift operation, all bits of the source 1 and destination operands are activated. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either a register or immediate operand. The available shift range is from –32 to +32.
Page 161: Figure 3.10 Logical Shift Operation Flow
Overflow Protection: The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section 3.1.8, Overflow Protection, for details. Logical Shift: Figure 3.10 shows the logical shift operation flow. Left Shift 0g 31 16 15 Shift out 0g 31 Shift amount data:...
Page 162: Most Significant Bit Detection Operation
Section 3 DSP Operation 1. Carry or Borrow Mode: CS[2:0] = 000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = 001 Bit 31 of the operation result is loaded into the DC bit. 3.
Page 163: Figure 3.11 Pdmsb Operation Flow
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. In case of an unconditional operation, they are always updated with the operation result.
Page 164: Table 3.8 Operation Definition Of Pdmsb
Section 3 DSP Operation Table 3.8 Operation Definition of PDMSB Source Data Guard Bit Upper Word 7g 6g … 1g 0g 31 30 29 28 … 0 … 0 … 0 … 0 … 0 … 0 … 0 … 0 …...
Page 165: Rounding Operation
Table 3.9 Variation of PDMSB Operation Mnemonic Function PDMSB MSB detection The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits.
Page 166: Figure 3.12 Rounding Operation Flow
Section 3 DSP Operation Guard Source 1 or 2 Figure 3.12 Rounding Operation Flow Figure 3.13 Definition of Rounding Operation Table 3.10 Variation of Rounding Operation Mnemonic Function PRND Rounding Overflow Protection: The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.1.8, Overflow Protection, for details.
Page 167: Overflow Protection
3.1.8 Overflow Protection The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the SH's standard multiply and MAC operations. The S bit in SR, in SH's CPU core, is used as the overflow protection enable bit.
Page 168: Data Transfer Operation
Section 3 DSP Operation 3.1.9 Data Transfer Operation This LSI can execute a maximum of two data transfer operations between the DSP register and the on-chip data memory in parallel for the DSP unit. Three types of data transfer instructions are provided for the DSP unit.
Page 169: Figure 3.14 Data Transfer Operation Flow
X pointer (R4, R5) XAB [15:1] X memory (RAM, ROM) XDB [15:0] Not affected for store and cleared for load Figure 3.14 Data Transfer Operation Flow Type 2 instructions execute just two data transfer operations. The 16-bit instruction code is used for this type of instructions.
Page 170: Figure 3.15 Single Data-Transfer Operation Flow (Word)
Section 3 DSP Operation Note: Data transfer by an LDS or STS instruction is possible since DSR is defined as a system register. Not affected for store and cleared for load See description of A0G and A1G. Figure 3.15 Single Data-Transfer Operation Flow (Word) Rev.
Page 171: Figure 3.16 Single Data-Transfer Operation Flow (Longword)
Figure 3.16 Single Data-Transfer Operation Flow (Longword) All data transfer operations are executed in the MA stage of the pipeline. All data transfer operations do not update any condition code bits in DSR. Pointer (R2, R3, R4, R5) LAB [31:0] Any memory areas LDB [31:0] Cannot be specified...
Page 172: Local Data Move Instruction
Section 3 DSP Operation 3.1.10 Local Data Move Instruction The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in order to support SH's standard multiply/MAC operations. They can be also used as temporary storage registers by local data move instructions between MACH/L and other DSP registers Figure 3.17 shows the flow of seven local data move instructions.
Page 173: Operand Conflict
3.1.11 Operand Conflict When an identical destination operand is specified with multiple parallel instructions, data conflict occurs. Table 3.14 shows the correspondence between each operand and registers. Table 3.14 Correspondence between Operands and Registers X-Memory Load Registers Notes: 1. Registers available for operands 2.
Page 174: Dsp Addressing
Section 3 DSP Operation DSP Addressing 3.2.1 DSP Repeat Control This LSI prepares a special control mechanism for efficient repeat loop control. An instruction SETRC sets the repeat times into the repeat counter RC (12 bits), and an execution mode in which a program loop executes repetitively until RC is equal to 1.
Page 175: Table 3.15 Address Value To Be Stored Into Spc (1)
#imm is 8 bits while RC is 12 bits. Therefore, to set more than 256 into RC, use Rm. A sample program is shown below. LDRS RptStart; LDRE RptEnd3+4; SETRC #imm; instr0; ; instr1–5 executes repeatedly RptStart: instr1; RptEnd3: instr2; instr3;...
Page 176: Table 3.16 Address Value To Be Stored Into Spc (2)
Section 3 DSP Operation 5. If a repeat loop has four or more instructions in it, any branch instructions (BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR and JMP), repeat control instructions (SETRC, LDRS and LDRE), load instructions for SR, RS, RE, and the TRAPA instruction must not be written within the last three instructions from the bottom of a repeat loop.
Page 177 In figure 3.18, exceptions generated by instructions marked as B and C are handled as follows: • Interrupt and DMA address errors An exception is accepted at neither instruction B or C, and the request is not even saved. A request is detected for the first time and accepted when the next instruction A is executed.
Page 178: Figure 3.18 Restriction Of Interrupt Acceptance In Repeat Loop
Section 3 DSP Operation A: Acceptable for any interrupts B and C: Acceptable for some interrupts RC > 1 : 1. 1 repeated step instr – 1 instr0 Start(End): instr1 instr2 4. 4 repeated steps instr – 1 instr0 Start: instr1 instr2 instr3...
Page 179 Based on this table, the actual repeat programming for various cases should be described as in the following examples: CASE 1: 1 Repeated Instruction LDRS LDRE SETRC - - - - RptStart0: instr0; RptStart: instr1; instr2; CASE 2: 2 Repeated Instructions LDRS LDRE SETRC...
Page 180 Section 3 DSP Operation CASE 4: 4 or More Repeated Instructions LDRS LDRE SETRC - - - - RptStart0: instr0; RptStart: instr1; instr2; instr3; ---------------------------------------------------------- RptEnd3: instrN-3; instrN-2; instrN-1; RptEnd: instrN; instrN+1; The examples above can be used as a template to program this repeat loop sequences. However, for easy programming, an extended instruction REPEAT is provided to handle these complex labeling and offset issues.
Page 181 CASE 1: 1 Repeated Instruction REPEAT RptStart, RptStart, RptCount; - - - - instr0; RptStart: instr1; instr2; CASE 2: 2 Repeated Instructions REPEAT RptStart, RptEnd, RptCount; - - - - instr0; RptStart: instr1; RptEnd: instr2; CASE 3: 3 Repeated Instructions REPEAT RptStart, RptEnd, RptCount;...
Page 182: Dsp Data Addressing
Section 3 DSP Operation CASE 4: 4 or More Repeated Instructions REPEAT RptStart, RptEnd, RptCount; - - - - instr0; RptStart instr1; instr2; instr3; ---------------------------------------------------------- instrN-3; instrN-2; instrN-1; RptEnd instrN; instrN+1; The expanded results of each case corresponds to the same case numbers in note 1. 3.2.2 DSP Data Addressing This LSI has two types of memory access instructions: one type is X and Y data transfer...
Page 183: Table 3.18 Summary Of Dsp Data Transfer Instructions
Table 3.18 Summary of DSP Data Transfer Instructions X and Y Data Transfer Operation (MOVX.W and MOVY.W) Address registers Ax: R4 and R5, Ay: R6 and R7 Index register(s) Ix: R8, Iy: R9 Addressing Not update/Increment (+2)/ operations Add-index-register Post-update Modulo addressing Data bus XDB and YDB...
Page 184: Figure 3.19 Dsp Addressing Instructions For Movx.w And Movy.w
Section 3 DSP Operation R8 [Ix] +2 (INC) +0 (Not update) Three address operation types: 1. Not update 2. Add-index-register (Ix/Iy) 3. Increment All operations are post-update type. To decrement an address pointer, set –2 in an index register. Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.W Addressing in X and Y data transfer operation is always word mode;...
Page 185: Figure 3.20 Dsp Addressing Instructions For Movs
–2/–4 (DEC) +2/+4 (INC) +0 (No update) Figure 3.20 DSP Addressing Instructions for MOVS Modulo Addressing: This LSI provides modulo addressing mode, which is common in DSPs. In modulo addressing mode, the address register is updated as explained above. When the address pointer reaches the pre-defined address (modulo-end address), it goes to the modulo start address.
Page 186: Figure 3.21 Modulo Addressing
Section 3 DSP Operation MS and ME are set to specify the start and end addresses, and then later to set the DMX or DMY bit to 1. When the X/Y data transfer instruction set in DMX/DMY is executed, the address register contents before update are compared with ME* in the address register as the updated value* specified for the X/Y data transfer instruction, the address pointer will not return to modulo start...
Page 187 An example is shown below. MS=H'7000; ME=H'7004; R4=H'A5007000; DMX=1; DMY=0 (modulo addressing for address register Ax) As a result of the above settings, the R4 register changes as follows. ; R4: H'A5007000 (Initial value) ; R4: H'A5007000 → H'A5007002 MOVX.W @R4+,Dx ;...
Page 188 Section 3 DSP Operation Addressing Instructions in Execution Stage: Address instructions, including modulo addressing, are executed in the execution stage of the pipeline. Behavior of the DSP data addressing in the execution stage is shown below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax;...
Page 189 /* The value to be added to the address register depends on addressing instructions. For example, (+2 or R8[Ix] or +0) means that if instruction is increment R8[Ix]: if instruction is add-index-register if instruction is not-update function modulo ( AddrReg, Index ) { if ( AddrReg[15:1]==ME[15:1] ) AddrReg[15:1]==MS[15:1];...
Page 190: Figure 3.22 Load/Store Control For X And Y Data-Transfer Instructions
Section 3 DSP Operation Instruction code for X data-transfer operation Input/output control for Control DSP data for X memory registers X0/X1, A0/A1 X_MEM X R/W X_MEM and Y_MEM: Select X and Y data memory Figure 3.22 Load/Store Control for X and Y Data-Transfer Instructions Control for X Memory: if ( !Nop ) { X_MEM=1;...
Page 191: Figure 3.23 Load/Store Control For Single-Data Transfer Instruction
Single-Data Transfer Instructions (MOVS.W and MOVS.L): This LSI has single load/store instructions for the DSP registers. It is similar to a load/store instruction for a system register. It transfers data between memory and DSP data registers using LAB and LDB buses. There may be access conflict between data access and instruction fetch.
Page 192 Section 3 DSP Operation Control LAB=MAB; if ( Ms!=NLS && W/L is word access ) { /* MOVS.W */ if (LS==load) { else { /* Store */ else if ( MA!=NLS && W/L is long-word access ) { /* MOVS.L */ if (LS==load) { else { /* Store */ Rev.
Page 193: Section 4 Clock Pulse Generator (Cpg)
Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), and a bus clock (Bφ). The CPG consists of an oscillator, PLL circuit, and divider circuit. Features The CPG has the following features.
Page 194: Figure 4.1 Block Diagram Of Clock Pulse Generator
Section 4 Clock Pulse Generator (CPG) CKIO CKIO2 Crystal XTAL oscillator EXTAL Clock frequency control circuit FRQCR [Legend] FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 STBCR3: Standby control register 3 STBCR4: Standby control register 4 Figure 4.1 Block Diagram of Clock Pulse Generator Rev.
Page 195 Section 4 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: PLL Circuit 1: PLL circuit 1 doubles, triples, or quadruples, the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin.
Page 196: Input/Output Pins
Section 4 Clock Pulse Generator (CPG) Input/Output Pins Table 4.1 lists the CPG pins and their functions. Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol I/O Mode control pins Crystal input/output pins XTAL (Clock input pins) EXTAL Clock input/output pin CKIO...
Page 197: Table 4.3 Relationship Between Clock Mode And Frequency Range
Mode 2: The frequency of the signal received from the EXTAL pin or crystal resonator LSI is quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This lowers the frequency required of the externally generated clock. Either a crystal resonator with a frequency in the range from 10 to 12.5 MHz or an external signal in the same frequency range input on the EXTAL pin may be used.
Page 198 Section 4 Clock Pulse Generator (CPG) PLL frequency multiplier Clock FRQCR operating register mode setting Circuit 1 Circuit 2 H'1303 ON (×4) ON (×2) H'1313 ON (×4) ON (×2) H'1333 ON (×4) ON (×2) H'1000 ON (×1) H'1001 ON (×1) H'1002 ON (×1) H'1003...
Page 199: Register Descriptions
Register Descriptions The CPG's control register is called the frequency control register (FRQCR). Refer the section 24, List of Registers, for the addresses of the registers and the state of each register in each processor state. 4.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock.
Page 200 Section 4 Clock Pulse Generator (CPG) Initial Bit Name Value  11, 10 All 0 STC1 STC0  7, 6 All 0 IFC1 IFC0  3, 2 All 0 PFC1 PFC0 Rev. 4.00 Sep. 14, 2005 Page 150 of 982 REJ09B0023-0400 Description Reserved...
Page 201: Changing The Frequency
Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are controlled by software through the frequency control register. The methods are described below. 4.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed.
Page 202: Notes On Board Design
Section 4 Clock Pulse Generator (CPG) Notes on Board Design Note on Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and feedback resistor R1 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground.
Page 203: Figure 4.3 Note On Using A Pll Oscillator Circuit
• A pair of Vss and Vcc for the input/output power supply nearest the USB module H3 to H4 • A pair of Vss and Vcc for the A/D converter. W19 to U20 Notes on Using a PLL Oscillator Circuit: In the Vcc and Vss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference.
Page 204 Section 4 Clock Pulse Generator (CPG) Rev. 4.00 Sep. 14, 2005 Page 154 of 982 REJ09B0023-0400...
Page 205: Section 5 Watchdog Timer (Wdt)
Section 5 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), which enables reset the LSI on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT is a single channel timer that counts up the clock-settling period when the system leaves standby mode or the temporary periods on standby that occur when the clock frequency is changed.
Page 206: Register Descriptions
Section 5 Watchdog Timer (WDT) Figure 5.1 shows a block diagram of the WDT. Standby Standby cancellation control Internal reset control request Interrupt Interrupt request control [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Figure 5.1 Block Diagram of the WDT Register Descriptions The WDT has the following two registers.
Page 207: Watchdog Timer Control/Status Register (Wtcsr)
5.2.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. The WTCSR register holds its value in an internal reset due to WDT overflow. The WTCSR register is initialized to H'00 only by a power-on reset caused by the RESETP pin.
Page 208 Section 5 Watchdog Timer (WDT) Initial Bit Name Value WOVF IOVF CKS2 CKS1 CKS0 Rev. 4.00 Sep. 14, 2005 Page 158 of 982 REJ09B0023-0400 Description Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode.
Page 209: Notes On Register Access
5.2.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction.
Page 210: Changing The Frequency
Section 5 Watchdog Timer (WDT) 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt processing program and this will stop the WDT.
Page 211: Using Interval Timer Mode
5.3.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT.
Page 212 Section 5 Watchdog Timer (WDT) Rev. 4.00 Sep. 14, 2005 Page 162 of 982 REJ09B0023-0400...
Page 213: Section 6 Power-Down Modes
Section 6 Power-Down Modes In the low power-consumption modes, operation of some of the internal peripheral modules and of the CPU stops. This leads to reduced power consumption. These modes are canceled by a reset or interrupt. Features 6.1.1 Power-Down Modes This LSI has the following power-down modes and function: 1.
Page 214: Reset
Section 6 Power-Down Modes Table 6.1 States of Power-Down Modes Mode Transition Conditions Sleep mode Execute SLEEP instruction with STBY bit cleared to 0 in STBCR Standby mode Execute SLEEP instruction with STBY bit set to 1 in STBCR Module standby Set the MSTP bits in function STBCR, STBCR2,...
Page 215: Input/Output Pins
• Manual-on reset 1. A low signal is input to the RESETM pin. 2. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1. 6.1.3 Input/Output Pins Table 6.2 lists the pins used for the power-down modes. Table 6.2 Pin Configuration Pin Name...
Page 216: Register Descriptions
Section 6 Power-Down Modes Register Descriptions The following registers are used in the low power-consumption modes. For the addresses and access sizes of these registers, see section 24, List of Registers. • Standby control register (STBCR) • Standby control register 2 (STBCR2) •...
Page 217: Standby Control Register 2 (Stbcr2)
6.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a readable/writable 8-bit register that controls the operation of modules in the power-down mode. STBCR2 is initialized (to H'00) by a power-on reset but retains its previous value after a manual reset or a period in the standby mode. Only byte access is valid.
Page 218: Standby Control Register 3 (Stbcr3)
Section 6 Power-Down Modes Initial Bit Name Value MSTP5 MSTP4 MSTP3 6.2.3 Standby Control Register 3 (STBCR3) STBCR3 is a readable/writable 8-bit register used to select whether or not individual modules operate in power-down mode. STBCR3 is initialized (to H'00) by a power-on reset, but retains its previous value after a manual reset or a period in the standby mode.
Page 219 Initial Bit Name Value  MSTP35  MSTP33 MSTP32 MSTP31 MSTP30 Description Reserved This bit is always read as 0. The write value should always be 0. Module Stop 35 When the MSTP35 bit is set to 1, supply of the clock to the CMT0 stops.
Page 220: Standby Control Register 4 (Stbcr4)
Section 6 Power-Down Modes 6.2.4 Standby Control Register 4 (STBCR4) STBCR4 is a readable/writable 8-bit register used to select whether or not individual modules operate in power-down mode. STBCR4 is initialized (to H'00) by a power-on reset, but retains its previous value after a manual reset or a period in the standby mode.
Page 221: Operation
Operation 6.3.1 Sleep Mode 1. Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules continue to run in sleep mode, but the on-chip memory is not accessible.
Page 222: Standby Mode
Section 6 Power-Down Modes 6.3.2 Standby Mode 1. Transition to Standby Mode The LSI switches from a program execution state to a standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR register. In standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
Page 223: Figure 6.1 Canceling Standby Mode With Stbcr.stby
2. Canceling Standby Mode Standby mode is canceled by interrupts (NMI, IRQ) or a reset. • Canceling with an Interrupt The on-chip WDT can be used for hot starts. When an interrupt request is detected at the rising or falling edge of NMI or IRQ, the clock will be supplied to the entire chip and standby mode canceled after the time set in the WDT's timer control/status register has elapsed.
Page 224: Module Standby Function
Section 6 Power-Down Modes 6.3.3 Module Standby Function 1. Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules (however, the initial state of the USB stops). This function can be used to reduce the power consumption in normal mode and sleep mode.
Page 225: Figure 6.2 Status Output At Manual Reset
1. Manual Reset CKIO RESETM normal STATUS Notes 1. In manual reset, STATUS = HH (reset) after the current bus cycle is completed and then internal reset is initiated. 2. reset: HH (STATUS1 = High, STATUS0 = High) 3. normal: LL (STATUS1 = Low, STATUS0 = Low) 4.
Page 226: Figure 6.4 Status Output When Software Standby Mode Is Canceled By A Manual Reset
Section 6 Power-Down Modes B Standby mode is canceled by a manual reset Oscillation stops CKIO RESETM normal STATUS Notes: If a standby mode is canceled by a manual reset, the WDT stops counting. RESETM must be kept low for the PLL oscillation stabilization time. reset : HH (STATUS1 = High, STATUS0 = High) standby : LH (STATUS1 = Low, STATUS0 = High) normal : LL (STATUS1 = Low, STATUS0 = Low)
Page 227: Figure 6.6 Status Output When Sleep Mode Is Canceled By A Manual Reset
B Sleep standby mode is canceled by a manual reset CKIO RESETM normal STATUS Notes: 1. RESETM must be kept low until STATUS = reset. 2. reset:HH (STATUS1 = High, STATUS0 = High) 3. sleep:HL(STSTUS1= High, STATUS0= Low) 4. normal:LL (STATUS1 = Low, STATUS0 = Low) 5.
Page 228 Section 6 Power-Down Modes Rev. 4.00 Sep. 14, 2005 Page 178 of 982 REJ09B0023-0400...
Page 229: Section 7 Cache
Features The cache specifications are listed in table 7.1. Table 7.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instructions/data mixed, 4-way set associative Locking Way 2 and way 3 are lockable Line size 16 bytes Number of entries 256 entries/way Write system P0, P1, P3: Write-back/write-through selectable Replacement method...
Page 230: Cache Structure
Section 7 Cache 7.1.1 Cache Structure The cache mixes data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries.
Page 231: Table 7.3 Lru And Way Replacement
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset, standby mode, module standby mode, and sleep mode. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11 to 4) can be registered in the cache.
Page 232: Register Descriptions
Section 7 Cache Register Descriptions The cache has the following registers. • Cache control register 1 (CCR1) • Cache control register 2 (CCR2) 7.2.1 Cache Control Register 1 (CCR1) The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has the CF bit (which invalidates all cache entries), and the WT and WB bits (which select either write-through mode or write-back mode).
Page 233: Cache Control Register 2 (Ccr2)
Initial Bit Name Value 7.2.2 Cache Control Register 2 (CCR2) CCR2 is used to enable or disable the cache locking function and is valid in cache locking mode only. In cache locking mode, the DSP bit (bit 12) in the status register (SR) of the CPU is set to 1. Alternatively, the lock enable bit (bit 16) in CCR2 is set to 1.
Page 234 Section 7 Cache Initial Bit Name value  31 to 17 All 0  15 to 10 All 0 W3LOAD W3LOCK  7 to 2 All 0 W2LOAD W2LOCK Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time. Rev.
Page 235: Table 7.4 Way To Be Replaced When A Cache Miss Occurs In Pref Instruction
Table 7.4 Way to be Replaced when a Cache Miss Occurs in PREF Instruction Cache Locking Mode Bit W3LOAD W3LOCK [Legend] Don't care Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time. Table 7.5 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction Cache Locking...
Page 236: Cache Operation
Section 7 Cache Table 7.7 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1) LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 7.8 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) LRU (Bits 5 to 0)
Page 237: Figure 7.2 Cache Search Scheme
Address 12 11 4 3 2 1 0 Entry selection Address array V U Tag address Physical address CMP0 CMP1 CMP2 CMP3 Hit signal (1) [Legend] CMP0: Comparison circuit for way 0 CMP1: Comparison circuit for way 1 CMP2: Comparison circuit for way 2 CMP3: Comparison circuit for way 3 Figure 7.2 Cache Search Scheme Longword (LW) selection...
Page 238: Read Access
Section 7 Cache 7.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. Read Miss: An external bus cycle starts and the entry is updated. The way replaced follows table 7.5.
Page 239: Write-Back Buffer
7.3.5 Write-Back Buffer When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory.
Page 240: Memory-Mapped Cache
Section 7 Cache Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The cache is mapped onto the P4 area. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF.
Page 241: Figure 7.4 Specifying Address And Data For Memory-Mapped Cache Access
Data Array Read: The data specified by L (bits 3 and 2) in the address is read from the entry address specified by the address and the entry corresponding to the way. Data Array Write: The longword data specified by the data is written to the position specified by L (bits 3 and 2) in the address from the entry address specified by the address and the entry corresponding to the way.
Page 242: Usage Examples
Section 7 Cache 7.4.3 Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found.
Page 243: Section 8 X/Y Memory
This LSI has on-chip X-RAM and Y-RAM. It can be used by CPU, DSP and DMAC to store instructions or data. Features The X/Y Memory features are listed in table 8.1. Table 8.1 X/Y Memory Specifications Parameter Features Addressing method Mapping is possible in space P0 or P2 Ports 3 independent read/write ports •...
Page 244: X/Y Memory Access From Cpu
Section 8 X/Y Memory X/Y Memory Access from CPU The X/Y memory can be accessed by the CPU from spaces P0 and P2. Access from space P0 uses the I bus, and access from space P2 use the L bus. To use the L bus, one cycle access is performed unless page conflict occurs.
Page 245: X/Y Memory Access From Dmac
X/Y Memory Access from DMAC The X/Y memory can be accessed by the DMAC via the I bus. Use the addresses between H'05007000 and H'05008FFF or H'05017000 and H'05018FFF. Usage Note When accessing the X/Y memory from the CPU and DSP, if the cache is on, access must be performed from space P2 (non-cacheable space).
Page 246 Section 8 X/Y Memory Rev. 4.00 Sep. 14, 2005 Page 196 of 982 REJ09B0023-0400...
Page 247: Section 9 Exception Handling
Section 9 Exception Handling Section 9 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing.
Page 248: Register Descriptions
Section 9 Exception Handling Register Descriptions There are three registers for exception handling. A register with an undefined initial value should be initialized by the software. • TRAPA exception register (TRA) • Exception event register (EXPEVT) • Interrupt event register 2 (INTEVT2) Figure 9.1 shows the bit configuration of each register.
Page 249: Exception Event Register (Expevt)
9.1.2 Exception Event Register (EXPEVT) EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of EXPEVT can be re-written using the software.
Page 250: Exception Handling Function
Section 9 Exception Handling Exception Handling Function 9.2.1 Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address.
Page 251: Exception Vector Addresses
The above operations from 1 to 3 are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction, a status different from that in effect before the exception handling can also be specified. Note: For details on the CPU processing mode in which RTE delay slot instructions are executed, please refer to section 9.6, Usage Notes.
Page 252: Exception Source Acceptance Timing And Priority
Section 9 Exception Handling other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and this status is not detected by an external device. To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0.
Page 253 If multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. A processing-completion type exception generated at the previous instruction* 2. A user break before instruction execution (re-execution type) 3. An exception related to an instruction fetch (CPU address error: re-execution type) 4.
Page 254 Section 9 Exception Handling Table 9.1 Exception Event Vectors Exception Current Type Instruction Exception Event Reset Aborted Power-on reset Manual reset H-UDI reset General Re-executed User break exception (before instruction execution) events CPU address error (instruction access) * Illegal general instruction exception Illegal slot instruction exception CPU address error (data access)* Completed...
Page 255: Individual Exception Operations
Individual Exception Operations This section describes the conditions for specific exception handling, and the processor operations. 9.3.1 Resets Power-On Reset: • Conditions Power-on reset is request • Operations Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the reset vector H'A0000000.
Page 256: General Exceptions
Section 9 Exception Handling Table 9.2 Type of Reset Type Condition to reset RESETP = Low level Power-on reset RESETM = Low level Manual reset H-UDI reset H-UDI reset command entry 9.3.2 General Exceptions CPU address error: • Conditions  Instruction is fetched from odd address (4n + 1, 4n + 3) ...
Page 257 Illegal general instruction exception: • Conditions  When undefined code not in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For details on undefined code, refer to SH-3/SH-3E/SH-3DSP Software Manual. When an undefined code other than H'FC00 to H'FFFF is decoded, operation cannot be guaranteed.
Page 258 Section 9 Exception Handling Unconditional trap: • Conditions TRAPA instruction executed • Types Instruction synchronous, processing-completion type • Save address An address of an instruction following TRAPA • Exception code H'160 • Remarks The exception is a processing-completion type, so PC of the instruction after the TRAPA instruction is saved to SPC.
Page 259 DMA address error: • Conditions  Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)  Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) • Types Instruction synchronous, processing-completion type •...
Page 260: Exception Processing While Dsp Extension Function Is Valid
Section 9 Exception Handling Exception Processing While DSP Extension Function is Valid When the DSP extension function is valid (the DSP bit of SR is set to 1), some exception processing acceptance conditions or exception processing may be changed. 9.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception In the DSP mode, a DSP extension instruction can be executed.
Page 261 • Example 1: Repeat loop consisting of four instructions LDRS RptStart LDRS RptDtct + 4 ; [A] SETRCT #4 instr0 RptStart: instr1 ……… ……… RptDtct: RptDtct RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext • Example 2: Repeat loop consisting of three instructions LDRS RptDtct + 4 LDRS...
Page 262 Section 9 Exception Handling • Example 3: Repeat loop consisting of two instructions LDRS RptDtct + 6 LDRS RptDtct + 4 SETRCT #4 RptDtct: RptDtct RptStart: RptDtct1 RptEnd: RptDtct3 InstrNext • Example 4: Repeat loop consisting of one instruction LDRS RptDtct + 8 LDRS RptDtct + 4...
Page 263: Table 9.4 Spc Value When A Re-Execution Type Exception Occurs In Repeat Control
Table 9.4 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control Instruction Where an Exception Occurs RptDtct RptDtct RptDtct1 RptDtct1  RptDtct2  RptDtct3 Note: The following labels are used here. RptDtct: Repeat detection instruction address RptDtct1: An instruction address one instruction following the repeat detection instruction RptDtct2: An instruction address two instruction following the repeat detection instruction RptDtct3: An instruction address three instruction following the repeat detection instruction Repeat start instruction address...
Page 264: Table 9.5 Exception Acceptance In The Repeat Loop
Section 9 Exception Handling An Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some exception will be retained to prevent an exception acceptance at an instruction where returning from the exception cannot be performed correctly. For details, refer to repeat loop program example 1 to 4.
Page 265: Table 9.6 Instruction Where A Specific Exception Occurs When A Memory Access Exception Occurs In Repeat Control
CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT.
Page 266: Note On Initializing This Lsi
Section 9 Exception Handling Note on Initializing this LSI This LSI needs to be initialized by a software reset before the power is turned on. Execute the following program immediately after a power-on reset. Note that the following program overwrites contents of CPU general registers. Save contents of registers which should not be overwritten before executing the following program.
Page 267 ;----------------------------------------------------------- ; Intialization of sh7641 for power-on reset ;----------------------------------------------------------- ; ATTENTION: 1. Please execute below instructions on power-on reset. 2. This routine would overwrite the general registers on the CPU. 3. Do not modify these codes. ;----------------------------------------------------------- MOV.L #H'A5007000,R4; MOV.L #H'A5008000,R5;...
Page 268: Usage Notes
Section 9 Exception Handling Usage Notes 1. An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according to the SR before restore.
Page 269: Section 10 Interrupt Controller (Intc)
Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 10.1 Features The INTC has the following features:...
Page 270: Figure 10.1 Block Diagram Of Intc
Section 10 Interrupt Controller (INTC) Figure 10.1 shows a block diagram of the INTC. IRQ7 to IRQ0 (Interrupt request) DMAC (Interrupt request) SCIF0 to 2 (Interrupt request) (Interrupt request) (Interrupt request) CMT0 and CMT1 (Interrupt request) MTU0 to MTU4 (Interrupt request) (Interrupt request) H-UDI (Interrupt request)
Page 271: Input/Output Pins
10.2 Input/Output Pins Table 10.1 shows the INTC pin configuration. Table 10.1 Pin Configuration Name Nonmaskable interrupt input pin NMI Interrupt input pins 10.3 Register Descriptions The INTC has the following registers. For details on register addresses and register states during each processing, refer to section 24, List of Registers.
Page 272 Section 10 Interrupt Controller (INTC) • Interrupt mask register 6 (IMR6) • Interrupt mask register 7 (IMR7) • Interrupt mask register 8 (IMR8) • Interrupt mask register 9 (IMR9) • Interrupt mask register 10 (IMR10) • Interrupt mask clear register 0 (IMCR0) •...
Page 273: Interrupt Priority Registers B To J (Iprb To Iprj)
10.3.1 Interrupt Priority Registers B to J (IPRB to IPRJ) IPRB to IPRJ are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module and IRQ interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode.
Page 274: Table 10.2 Interrupt Sources And Iprb To Iprj
Section 10 Interrupt Controller (INTC) Table 10.2 Interrupt Sources and IPRB to IPRJ Register Bits 15 to 12 IPRB IPRC IRQ3 IPRD IRQ7 IPRE Reserved* IPRF ADC1 IPRG MTU0 (A/B/C/D) IPRH MTU2 (A/B) IPRI MTU4 (A/B/C/D) IPRJ DMAC0 Note: Reserved: These bits are always read as 0. The write value should always be 0. As shown in table 10.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit groups in each register.
Page 275: Interrupt Control Register 0 (Icr0)
10.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 276: Interrupt Control Register 1 (Icr1)
Section 10 Interrupt Controller (INTC) 10.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to IRQ0 individually: rising edge, falling edge, high level, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 277: Interrupt Control Register 3 (Icr3)
10.3.4 Interrupt Control Register 3 (ICR3) ICR3 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 and IRQ6 individually: rising edge, falling edge, high level, or low level. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Initial Bit Name Value...
Page 278: Interrupt Request Register 0 (Irr0)
Section 10 Interrupt Controller (INTC) 10.3.5 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 279: Interrupt Mask Registers 0 To 10 (Imr0 To Imr10)
10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10) IMR0 to IMR10 are 8-bit readable/writable registers that mask the IRQ and on-chip peripheral module interrupts. When an interrupt source is masked, interrupt requests may be mistakenly detected, depending on the operation state of the IRQ pins and on-chip peripheral modules. To prevent this, set IMR0 to IMR9 while no interrupts are set to be generated, and then read the new settings from these registers.
Page 280: Table 10.3 Correspondence Between Interrupt Sources And Imr0 To Imr10
Section 10 Interrupt Controller (INTC) Table 10.3 Correspondence between Interrupt Sources and IMR0 to IMR10 Register Name IMR0 IRQ7 IRQ6 (IRQ) (IRQ) IMR1 TxI0 BRI0 (SCIF0) (SCIF0)  IMR2 — (ADC0) (ADC0) IMR4 — — — — IMR5 TxI2 BRI2 (SCIF2) (SCIF2) IMR6...
Page 281: Interrupt Mask Clear Registers 0 To 10 (Imcr0 To Imcr10)
10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10) IMCR0 to IMCR10 are 8-bit writable registers that clear the mask settings for the IRQ and on- chip peripheral module interrupts. Table 10.4 shows the relationship between IMCR and each interrupt source.
Page 282: Table 10.4 Correspondence Between Interrupt Sources And Imcr0 To Imcr10
Section 10 Interrupt Controller (INTC) Table 10.4 Correspondence between Interrupt Sources and IMCR0 to IMCR10 Register Name IMCR0 IRQ7 IRQ6 (IRQ) (IRQ) IMCR1 TxI0 BRI0 (SCIF0) (SCIF0)  IMCR2 — (ADC0) (ADC0) IMCR4 — — — — IMCR5 TxI2 BRI2 (SCIF2) (SCIF2) IMCR6...
Page 283: Interrupt Sources
10.4 Interrupt Sources There are four types of interrupt sources: NMI, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an interrupt, so the interrupt request is ignored. 10.4.1 NMI Interrupt The NMI interrupt has the highest priority level of 16.
Page 284: On-Chip Peripheral Module Interrupts
Section 10 Interrupt Controller (INTC) Edge input interrupt detection requires input of a pulse width of more than two cycles on a P clock basis. When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU samples the pins.
Page 285: Interrupt Exception Handling And Priority
Section 10 Interrupt Controller (INTC) 10.4.5 Interrupt Exception Handling and Priority There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. The priority of each interrupt source is set within level 0 to level 16; level 16 is the highest and level 1 is the lowest.
Page 286: Table 10.5 Interrupt Exception Handling Sources And Priority
Section 10 Interrupt Controller (INTC) Table 10.5 Interrupt Exception Handling Sources and Priority Exception Interrupt Source Code H'1C0 H-UDI interrupt H'5E0 IRQ0 H'600 IRQ1 H'620 IRQ2 H'640 IRQ3 H'660 IRQ4 H'680 IRQ5 H'6A0 IRQ6 H'6C0 IRQ7 H'6E0 DMAC0 DEI0 H'800 DMAC1 DEI1 H'820 DMAC2 DEI2...
Page 287 Exception Interrupt Source Code MTU0 TGI0A H'A80 TGI0B H'AA0 TGI0C H'AC0 TGI0D H'AE0 TCI0V H'B00 MTU1 TGI1A H'C00 TGI1B H'C20 TCI1V H'C40 TCI1U H'C60 MTU2 TGI2A H'C80 TGI2B H'CA0 TCI2V H'CC0 TCI2U H'CE0 MTU3 TGI3A H'D00 TGI3B H'D20 TGI3C H'D40 TGI3D H'D60 TCI3V...
Page 288: Intc Operation
Section 10 Interrupt Controller (INTC) 10.5 INTC Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2.
Page 289: Figure 10.2 Interrupt Operation Flowchart
NMI? Set interrupt sourse in INTEVT2 Save SR to SSR; save PC to SPC Set BL/RB bits in SR to1 Branch to exception handler I3 to I0: Interrupt mask bits in status register (SR) Figure 10.2 Interrupt Operation Flowchart Section 10 Interrupt Controller (INTC) Program execution state Interrupt...
Page 290: Multiple Interrupts
Section 10 Interrupt Controller (INTC) 10.5.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT2. The code in INTEVT2 can be used as an offset for branching to the specific handler. 2.
Page 291: Section 11 User Break Controller (Ubc)
Section 11 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch.
Page 292: Figure 11.1 Block Diagram Of User Break Controller
Section 11 User Break Controller (UBC) Figure 11.1 shows a block diagram of the UBC. XAB/YAB Access ASID Control LDB/IDB/ XDB/YDB [Legend] Break bus cycle register A BBRA: Break address register A BARA: Break address mask register A BAMRA: Break ASID register A BASRA: Break bus cycle register B BBRB:...
Page 293: Register Descriptions
11.2 Register Descriptions The user break controller has the following registers. For details on register addresses and access sizes, refer to section 24, List of Registers. • Break address register A (BARA) • Break address mask register A (BAMRA) • Break bus cycle register A (BBRA) •...
Page 294: Break Address Mask Register A (Bamra)
Section 11 User Break Controller (UBC) 11.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Initial Bit Name Value 31 to 0 BAMA31 to All 0 BAMA0 11.2.3 Break Bus Cycle Register A (BBRA)
Page 295 Initial Bit Name Value IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Section 11 User Break Controller (UBC) Description Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle...
Page 296: Break Address Register B (Barb)
Section 11 User Break Controller (UBC) 11.2.4 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address buses for break condition B.
Page 297: Break Address Mask Register B (Bamrb)
11.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Initial Bit Name Value 31 to 0 BAMB31 to All 0 BAMB0 11.2.6 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register.
Page 298: Break Data Mask Register B (Bdmrb)
Section 11 User Break Controller (UBC) Table 11.2 Specifying Break Data Register Bus Selection in BBRB L bus I bus X bus Y bus Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2.
Page 299: Break Bus Cycle Register B (Bbrb)
11.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B.
Page 300 Section 11 User Break Controller (UBC) Initial Bit Name Value IDB1 IDB0 RWB1 RWB0 SZB1 SZB0 Rev. 4.00 Sep. 14, 2005 Page 250 of 982 REJ09B0023-0400 Description Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition.
Page 301: Break Control Register (Brcr)
11.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions.
Page 302 Section 11 User Break Controller (UBC) Initial Bit Name Value SCMFDA SCMFDB PCTE PCBA  9, 8 All 0 DBEB Rev. 4.00 Sep. 14, 2005 Page 252 of 982 REJ09B0023-0400 Description I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0).
Page 303 Initial Bit Name Value PCBB  5, 4 All 0  2, 1 All 0 ETBE Section 11 User Break Controller (UBC) Description PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction...
Page 304: Execution Times Break Register (Betr)
Section 11 User Break Controller (UBC) 11.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 –...
Page 305: Branch Destination Register (Brdr)
11.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset.
Page 306: Operation
Section 11 User Break Controller (UBC) 11.3 Operation 11.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses is set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB).
Page 307: Break On Instruction Fetch Cycle
 If a logical address issued on the L bus by the CPU is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued in longwords and its address is rounded to match longword boundaries.
Page 308: Break On Data Access Cycle
Section 11 User Break Controller (UBC) 4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus.
Page 309: Break On X/Y-Memory Bus Cycle
word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored). 4.
Page 310: Sequential Break
Section 11 User Break Controller (UBC) 11.3.5 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches.
Page 311: Pc Trace
4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the SPC. At which instruction the break occurs cannot be determined accurately.
Page 312: Usage Examples
Section 11 User Break Controller (UBC) 11.3.8 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) • Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 313 After an instruction with and address H'00037226 is executed, a user break occurs before an instruction with and address H'0003722E is executed. (Example 1-3) • Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 314 Section 11 User Break Controller (UBC) (Example 1-5) • Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 315 Break Condition Specified for L Bus Data Access Cycle: (Example 2-1) • Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 316: Usage Notes
Section 11 User Break Controller (UBC) Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) • Register specifications BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 317 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 9.1 in section 9, Exception Handling. If an exception with higher priority occurs, the user break is not generated.
Page 318 Section 11 User Break Controller (UBC) Rev. 4.00 Sep. 14, 2005 Page 268 of 982 REJ09B0023-0400...
Page 319: Section 12 Bus State Controller (Bsc)
Section 12 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 12.1 Features The BSC has the following features:...
Page 320 Section 12 Bus State Controller (BSC)  Supports low-frequency and power-down modes.  Issues MRS and EMRS commands. 6. Byte-selection SRAM interface  Can connect directly to a byte-selection SRAM 7. Burst MPX-IO interface  Can connect directly to a peripheral LSI that needs an address/data multiplexing. ...
Page 321: Figure 12.1 Bsc Functional Block Diagram
BSC functional block diagram is shown in figure 12.1. BACK BREQ WAIT CS0, CS2, CS3, CS4, CS5A, CS5B, CS6A, CS6B A25 to A0, D31 to D0 BS, RD/WR, RD, WE3 to WE0, RASU, RASL, CASU, CASL CKE, DQMxx, AH, FRAME [Legend] CMNCR: Common control register...
Page 322: Input/Output Pins
Section 12 Bus State Controller (BSC) 12.2 Input/Output Pins Table 12.1 shows pin configuration of the BSC. Table 12.1 Pin Configuration Name A25 to A0 Output D31 to D0 Output CS0, CS2 to CS4 Output CS5A Output RD/WR Output Output WE3/ICIOWR/AH Output WE2/ICIRD...
Page 323: Area Overview
Name Output RASU Output RASL CASU Output CASL Output FRAME Output WAIT Input BREQ Input BACK Output Input 12.3 Area Overview 12.3.1 Area Division In the architecture of this LSI, both logical spaces and physical spaces have 32-bit address spaces. The cache access method is shown by the upper three bits.
Page 324: Shadow Area
Section 12 Bus State Controller (BSC) 12.3.2 Shadow Area Areas 0, 2 to 4, 5A, 5B, 6A, and 6B are decoded by addresses A28 to A26, which correspond to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space between P0 and P3 obtained by adding to it H'20000000 ×...
Page 325: Address Map
12.3.3 Address Map The external address space has a capacity of 384 Mbytes and is used by dividing 8 partial spaces. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 12.2 Address Space Map 1 (CMNCR.MAP = 0) Physical Address H'00000000 to H'03FFFFFF...
Page 326: Table 12.3 Address Space Map 2 (Cmncr.map = 1)
Section 12 Bus State Controller (BSC) Table 12.3 Address Space Map 2 (CMNCR.MAP = 1) Physical Address Area H'00000000 to Area 0 H'03FFFFFF H'04000000 to Area 1 H'07FFFFFF H'08000000 to Area 2 H'0BFFFFFF H'0C000000 to Area 3 H'0FFFFFFF H'10000000 to Area 4 H'13FFFFFF H'14000000 to...
Page 327: Area 0 Memory Type And Memory Bus Width
12.3.4 Area 0 Memory Type and Memory Bus Width The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to select word (16 bits), or longword (32 bits) on power-on reset. The correspondence between the external pin MD3 and memory size is listed in the table below.
Page 328: Common Control Register (Cmncr)
Section 12 Bus State Controller (BSC) • Refresh timer control/status register (RTCSR) • Refresh timer counter (RTCNT) • Refresh time constant register (RTCOR) • Reset wait counter (RWTCNT) 12.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. This register is only initialized by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Page 329 Initial Bit Name Value BLOCK DPRTY1 DPRTY0 DMAIW2 DMAIW1 DMAIW0 Section 12 Bus State Controller (BSC) Description Bus Clock Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. DMA Burst Transfer Priority Specify the priority for a refresh request/bus mastership request during DMA burst transfer.
Page 330 Section 12 Bus State Controller (BSC) Initial Bit Name Value DMAIWA   CKD2RDV HIZMEM Rev. 4.00 Sep. 14, 2005 Page 280 of 982 REJ09B0023-0400 Description Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit.
Page 331: Csn Space Bus Control Register (Csnbcr) (N = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
Initial Bit Name Value HIZCNT 12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number of idle cycles between bus cycles, and the bus-width. This register is initialized to H'36DB0600 by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Page 332 Section 12 Bus State Controller (BSC) Initial Bit Name Value IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRWS1 IWRWS0 Rev. 4.00 Sep. 14, 2005 Page 282 of 982 REJ09B0023-0400 Description Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space.
Page 333 Initial Bit Name Value IWRRD2 WRRD1 IWRRD0 IWRRS2 IWRRS1 IWRRS0  Section 12 Bus State Controller (BSC) Description Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space.
Page 334 Section 12 Bus State Controller (BSC) Initial Bit Name Value TYPE2 TYPE1 TYPE0  Rev. 4.00 Sep. 14, 2005 Page 284 of 982 REJ09B0023-0400 Description Specify the type of memory connected to a space. 0000: Normal space 0001: Burst ROM (clock synchronous) 0010: MPX-I/O 0011: Byte-selection SRAM 0100: SDRAM...
Page 335 Initial Bit Name Value BSZ1 BSZ0  8 to 0 All 0 Note: The CS0CR samples the external pins (MD3) that specify the bus width at power-on reset. Section 12 Bus State Controller (BSC) Description Data Bus Size Specify the data bus sizes of spaces. The data bus sizes of areas 2, 3, 4 and 5A are shown below.
Page 336: Csn Space Wait Control Register (Csnwcr) (N = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
Section 12 Bus State Controller (BSC) 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) This register specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR).
Page 337 Initial Bit Name Value  5 to 2 All 0 Section 12 Bus State Controller (BSC) Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles...
Page 338 Section 12 Bus State Controller (BSC) Initial Bit Name Value Note: To connect the burst ROM to the CS0 area and use the burst ROM interface after the BSC is activated, enables the burst access through bit 20, specifies the number of burst wait cycles through bits 17 and 16, and then set the bits TYPE[2:0] in CS0BCR.
Page 339 Initial Bit Name Value  5 to 0 All 0 Section 12 Bus State Controller (BSC) Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles...
Page 340 Section 12 Bus State Controller (BSC) • CS4WCR Initial Bit Name Value  31 to 21 All 0   15 to 13 All 0 Rev. 4.00 Sep. 14, 2005 Page 290 of 982 REJ09B0023-0400 Description Reserved These bits are always read as 0. The write value should always be 0.
Page 341 Initial Bit Name Value Section 12 Bus State Controller (BSC) Description Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles...
Page 342 Section 12 Bus State Controller (BSC) Initial Bit Name Value  5 to 2 All 0 • CS5AWCR Initial Bit Name Value  31 to 19 All 0  15 to 13 All 0 Rev. 4.00 Sep. 14, 2005 Page 292 of 982 REJ09B0023-0400 Description Reserved...
Page 343 Initial Bit Name Value Section 12 Bus State Controller (BSC) Description Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles...
Page 344 Section 12 Bus State Controller (BSC) Initial Bit Name Value  5 to 2 All 0 • CS5BWCR Initial Bit Name Value  31 to 22 All 0 SZSEI Rev. 4.00 Sep. 14, 2005 Page 294 of 982 REJ09B0023-0400 Description Reserved These bits are always read as 0.
Page 345 Initial Bit Name Value   15 to 13 All 0 Section 12 Bus State Controller (BSC) Description MPX-IO Interface Address Wait Specifies the address cycle insertion wait for MPX-IO interface. This bit setting is valid only when area 5B is specified as MPX-I/O.
Page 346 Section 12 Bus State Controller (BSC) Initial Bit Name Value Rev. 4.00 Sep. 14, 2005 Page 296 of 982 REJ09B0023-0400 Description Number of Delay Cycles from Address, CSn Assertion to RD, WE Assertion Specify the number of delay cycles from address and CSn assertion to RD and WE assertion.
Page 347 Initial Bit Name Value  5 to 2 All 0 • CS6AWCR Initial Bit Name Value  31 to 13 All 0 Section 12 Bus State Controller (BSC) Description Reserved These bits are always read as 0. The write value should always be 0.
Page 348 Section 12 Bus State Controller (BSC) Initial Bit Name Value  5 to 2 All 0 Rev. 4.00 Sep. 14, 2005 Page 298 of 982 REJ09B0023-0400 Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access.
Page 349 Initial Bit Name Value • CS6BWCR Initial Bit Name Value  31 to 21 All 0  19 to 13 All 0 Section 12 Bus State Controller (BSC) Description Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation.
Page 350 Section 12 Bus State Controller (BSC) Initial Bit Name Value  5 to 2 All 0 Rev. 4.00 Sep. 14, 2005 Page 300 of 982 REJ09B0023-0400 Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access.
Page 351 Initial Bit Name Value Burst ROM (Clock Asynchronous): • CS0WCR Initial Bit Name Value  31 to 21 All 0  19, 18 All 0 Section 12 Bus State Controller (BSC) Description Number of Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD, WEn negation to address, and CSn negation.
Page 352 Section 12 Bus State Controller (BSC) Initial Bit Name Value  15 to 11 All 0 Rev. 4.00 Sep. 14, 2005 Page 302 of 982 REJ09B0023-0400 Description Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access.
Page 353 Initial Bit Name Value  5 to 0 All 0 • CS4WCR Initial Bit Name Value  31 to 21 All 0  19, 18 All 0 Section 12 Bus State Controller (BSC) Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0.
Page 354 Section 12 Bus State Controller (BSC) Initial Bit Name Value  15 to 13 All 0 Rev. 4.00 Sep. 14, 2005 Page 304 of 982 REJ09B0023-0400 Description Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access.
Page 355 Initial Bit Name Value  5 to 2 All 0 Section 12 Bus State Controller (BSC) Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles...
Page 356 Section 12 Bus State Controller (BSC) Initial Bit Name Value SDRAM*: • CS2WCR Initial Bit Name Value  31 to 11 All 0   A2CL1 A2CL0  6 to 0 All 0 Rev. 4.00 Sep. 14, 2005 Page 306 of 982 REJ09B0023-0400 Description Delay Cycles from RD, WEn Negation to Address, CSn...
Page 357 • CS3WCR Initial Bit Name Value  31 to 15 All 0 WTRP1* WTRP0  WTRCD1 WTRCD0 Section 12 Bus State Controller (BSC) Description Reserved These bits are always read as 0. The write value should always be 0. Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles during the periods shown below.
Page 358 Section 12 Bus State Controller (BSC) Initial Bit Name Value  A3CL1 A3CL0  6, 5 All 0 TRWL1* TRWL0 Rev. 4.00 Sep. 14, 2005 Page 308 of 982 REJ09B0023-0400 Description Reserved This bit is always read as 0. The write value should always be 0.
Page 359 Initial Bit Name Value  WTRC1* WTRC0 Note: If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or byte-selection SRAM. Burst MPX-IO: •...
Page 360 Section 12 Bus State Controller (BSC) Initial Bit Name Value MPXMD  Rev. 4.00 Sep. 14, 2005 Page 310 of 982 REJ09B0023-0400 Description Burst MPX-IO Interface Mode Specification Specify the access mode in 16-byte access 0: One 4-burst access by 16-byte transfer 1: Two 2-bursts accesses by quad word (8-byte) transfer Transfer size when MPXMD = 0...
Page 361 Initial Bit Name Value  15 to 11 All 0  5 to 0 All 0 Section 12 Bus State Controller (BSC) Description Reserved These bits are always read as 0. The write value should always be 0. Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle.
Page 362 Section 12 Bus State Controller (BSC) Burst ROM (Clock Synchronous): • CS0WCR Initial Bit Name Value  31 to 18 All 0  15 to 11 All 0 Rev. 4.00 Sep. 14, 2005 Page 312 of 982 REJ09B0023-0400 Description Reserved These bits are always read as 0.
Page 363 Initial Bit Name Value  5 to 0 All 0 Section 12 Bus State Controller (BSC) Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles...
Page 364: Sdram Control Register (Sdcr)
Section 12 Bus State Controller (BSC) 12.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Page 365 Initial Bit Name Value DEEP SLOW RFSH RMODE Section 12 Bus State Controller (BSC) Description Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low- power SDRAM enters the deep power-down mode.
Page 366 Section 12 Bus State Controller (BSC) Initial Bit Name Value PDOWN BACTV  7 to 5 All 0 A3ROW1 A3ROW0 Rev. 4.00 Sep. 14, 2005 Page 316 of 982 REJ09B0023-0400 Description Power-Down Mode Specifies whether the SDRAM will enter the power- down mode or not after the access to the external memory other than the SDRAM or to the internal I/O resister.
Page 367: Refresh Timer Control/Status Register (Rtcsr)
Initial Bit Name Value  A3COL1 A3COL0 12.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. This register is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Page 368 Section 12 Bus State Controller (BSC) Initial Bit Name Value  CKS2 CKS1 CKS0 RRC2 RRC1 RRC0 Rev. 4.00 Sep. 14, 2005 Page 318 of 982 REJ09B0023-0400 Description Reserved This bit is always read as 0. The write value should always be 0.
Page 369: Refresh Timer Counter (Rtcnt)
12.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection.
Page 370: Reset Wait Counter (Rwtcnt)
Section 12 Bus State Controller (BSC) 12.4.8 Reset Wait Counter (RWTCNT) RWTCNT is a 7-bit counter. This counter starts to increment by synchronizing the CKIO after a power-on reset is released, and stops when the value reaches H'007F. External bus access is suspended while the counter is operating.
Page 371: Operating Description
12.5 Operating Description 12.5.1 Endian/Access Size and Data Alignment This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the byte data. Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte- selection SRAM.
Page 372: Table 12.6 16-Bit External Device Access And Data Alignment
Section 12 Bus State Controller (BSC) Table 12.6 16-Bit External Device Access and Data Alignment D31 to D23 to Operation  Byte access at 0  Byte access at 1  Byte access at 2  Byte access at 3 ...
Page 373: Table 12.7 8-Bit External Device Access And Data Alignment
Table 12.7 8-Bit External Device Access and Data Alignment D31 to Operation  Byte access at 0  Byte access at 1  Byte access at 2  Byte access at 3  Word 1st time access at 0 at 0 ...
Page 374: Normal Space Interface
Section 12 Bus State Controller (BSC) 12.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte- selection pin, see section 12.5.8, Byte-Selection SRAM Interface.
Page 375: Figure 12.4 Continuous Access For Normal Space 1 Bus Width = 16 Bits, Longword Access, Csnwcr.wn Bit = 0 (Access Wait = 0, Cycle Wait = 0)
Section 12 Bus State Controller (BSC) It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Page 376: Figure 12.5 Continuous Access For Normal Space 2 Bus Width = 16 Bits, Longword Access, Csnwcr.wn Bit = 1 (Access Wait = 0, Cycle Wait = 0)
Section 12 Bus State Controller (BSC) Read D15 to D0 Write D15 to D0 Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WN Bit = 1 Rev. 4.00 Sep. 14, 2005 Page 326 of 982 REJ09B0023-0400 CKIO A25 to A0...
Page 377: Figure 12.6 Example Of 32-Bit Data-Width Sram Connection
This LSI Figure 12.6 Example of 32-Bit Data-Width SRAM Connection Section 12 Bus State Controller (BSC) 128k × 8-bit SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Rev. 4.00 Sep. 14, 2005 Page 327 of 982 REJ09B0023-0400...
Page 378: Figure 12.7 Example Of 16-Bit Data-Width Sram Connection
Section 12 Bus State Controller (BSC) This LSI Figure 12.7 Example of 16-Bit Data-Width SRAM Connection This LSI Figure 12.8 Example of 8-Bit Data-Width SRAM Connection Rev. 4.00 Sep. 14, 2005 Page 328 of 982 REJ09B0023-0400 128k × 8-bit SRAM I/O7 I/O0 I/O7...
Page 379: Access Wait Control
12.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in read access and in write access.
Page 380: Figure 12.10 Wait State Timing For Normal Space Access (Wait State Insertion Using Wait Signal)
Section 12 Bus State Controller (BSC) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software wait.
Page 381: Csn Assert Period Expansion
CSn Assert Period Expansion 12.5.4 The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained.
Page 382: Mpx-I/O Interface
Section 12 Bus State Controller (BSC) 12.5.5 MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5B, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space.
Page 383: Figure 12.13 Access Timing For Mpx Space (Address Cycle Wait 1, Data Cycle No Wait)
CKIO A25 to A16 RD/WR Read D7 to D0 or D15 to D0 Write D7 to D0 or D15 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) Tadw Address Address...
Page 384: Figure 12.14 Access Timing For Mpx Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
Section 12 Bus State Controller (BSC) CKIO A25 to A16 CS5B RD/WR Read D7 to D0 or D15 to D0 Write D7 to D0 or D15 to D0 WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.14 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) Rev.
Page 385: Sdram Interface
Section 12 Bus State Controller (BSC) 12.5.6 SDRAM Interface SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles.
Page 386: Figure 12.15 Example Of 32-Bit Data Width Sdram Connection (Rasu And Casu Are Not Used)
Section 12 Bus State Controller (BSC) Figures 12.15 to 12.17 show examples of the connection of the SDRAM with the LSI. As shown in figure 12.17, two sets of SDRAMs of 32 Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL.
Page 387: Figure 12.16 Example Of 16-Bit Data Width Sdram Connection (Rasu And Casu Are Not Used)
This LSI CKIO RASU Unused CASU Unused RASL CASL RD/WR DQMLU DQMLL Figure 12.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU are Not Used) Section 12 Bus State Controller (BSC) 64M SDRAM (1M × 16-bit × 4-bank) I/O15 I/O0 DQMU...
Page 388: Figure 12.17 Example Of 16-Bit Data Width Sdram Connection (Rasu And Casu Are Used)
Section 12 Bus State Controller (BSC) This LSI CKIO RASU CASU RASL CASL RD/WR DQMLU DQMLL Figure 12.17 Example of 16-Bit Data Width SDRAM Connection Rev. 4.00 Sep. 14, 2005 Page 338 of 982 REJ09B0023-0400 (RASU and CASU are Used) 64M SDRAM (1M ×...
Page 389 Section 12 Bus State Controller (BSC) Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 12.8 to 12.13 show the relationship between the settings of bits BSZ1 and BSZ0, AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins.
Page 390: Table 12.8 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (1)-1
Section 12 Bus State Controller (BSC) Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-1 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A22* A21* A20*...
Page 391: Table 12.8 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (1)-2
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (1)-2 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A23* A22* A20* Example of connected memory 128-Mbit product (1 Mword ×...
Page 392: Table 12.9 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (2)-1
Section 12 Bus State Controller (BSC) Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-1 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A24* A23* A20*...
Page 393: Table 12.9 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (2)-2
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (2)-2 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A25* A24* A20* Example of connected memory 512-Mbit product (4 Mwords ×...
Page 394 Section 12 Bus State Controller (BSC) Table 12.10 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A25* A24* A20* Example of connected memory...
Page 395: Table 12.11 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (4)-1
Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-1 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A21* A20* Example of connected memory 16-Mbit product (512 kwords ×...
Page 396: Table 12.11 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (4)-2
Section 12 Bus State Controller (BSC) Table 12.11 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (4)-2 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A22* A21* Example of connected memory...
Page 397: Table 12.12 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (5)-1
Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-1 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A22* A21* Example of connected memory 128-Mbit product (2 Mwords ×...
Page 398: Table 12.12 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (5)-2
Section 12 Bus State Controller (BSC) Table 12.12 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (5)-2 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A24* A23* Example of connected memory...
Page 399: Table 12.13 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (6)-1
Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-1 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A24* A23* A20* Example of connected memory 256-Mbit product (4 Mwords ×...
Page 400: Table 12.13 Relationship Between Bsz1, 0, A2/3Row1, 0, And Address Multiplex Output (6)-2
Section 12 Bus State Controller (BSC) Table 12.13 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output (6)-2 Setting A2/3 1, 0 1, 0 11 (32 bits) 00 (11 bits) Output Pin of Row Address This LSI Output Cycle A25* A24* A20*...
Page 401: Table 12.14 Relationship Between Access Size And Number Of Bursts
Burst Read: A burst read occurs in the following cases with this LSI. • Access size in reading is larger than data bus width. • 16-byte transfer in cache error. • 16-byte transfer in DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus.
Page 402: Figure 12.18 Burst Read Basic Timing (Cas Latency 1, Auto Pre-Charge)
Section 12 Bus State Controller (BSC) number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in the CS2WCR register or the A3CL1 and A3CL0 bits in the CS3WCR register and WTRCD0 bit in the CS3WCR register.
Page 403: Figure 12.19 Burst Read Wait Specification Timing (Cas Latency 2, Wtrcd1 And Wtrcd0 = 1 Cycle, Auto Pre-Charge)
CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.19 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD1 and WTRCD0 = 1 Cycle, Auto Pre-Charge) Rev.
Page 404: Figure 12.20 Basic Timing For Single Read (Cas Latency 1, Auto Pre-Charge)
Section 12 Bus State Controller (BSC) Single Read: A read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output.
Page 405 Section 12 Bus State Controller (BSC) Burst Write: A burst write occurs in the following cases in this LSI. • Access size in writing is larger than data bus width. • Write-back of the cache • 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1.
Page 406: Figure 12.21 Basic Timing For Burst Write (Auto Pre-Charge)
Section 12 Bus State Controller (BSC) CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge) Rev.
Page 407: Figure 12.22 Single Write Basic Timing (Auto-Precharge)
Single Write: A write access ends in one cycle when data is written in non-cacheable region and the data bus width is larger than or equal to access size. Figure 12.22 shows the single write basic timing. CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU...
Page 408 Section 12 Bus State Controller (BSC) Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3.
Page 409: Figure 12.23 Burst Read Timing (Bank Active, Different Bank, Cas Latency 1)
When bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 12.23 or 12.26, followed by repetition of the cycle in figure 12.24 or 12.27. An access to a different area during this time has no effect.
Page 410: Figure 12.24 Burst Read Timing (Bank Active, Same Row Addresses In The Same Bank, Cas Latency 1)
Section 12 Bus State Controller (BSC) CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) Rev.
Page 411: Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses In The Same Bank, Cas Latency 1)
CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) Section 12 Bus State Controller (BSC) Rev.
Page 412: Figure 12.26 Single Write Timing (Bank Active, Different Bank)
Section 12 Bus State Controller (BSC) CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Figure 12.26 Single Write Timing (Bank Active, Different Bank) Rev. 4.00 Sep. 14, 2005 Page 362 of 982 REJ09B0023-0400 Notes: 1.
Page 413: Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses In The Same Bank)
CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) Tnop 2.
Page 414: Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses In The Same Bank)
Section 12 Bus State Controller (BSC) CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. (Bank Active, Different Row Addresses in the Same Bank) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing.
Page 415 Section 12 Bus State Controller (BSC) 1. Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used.
Page 416: Figure 12.29 Auto-Refresh Timing
Section 12 Bus State Controller (BSC) CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* 2. Self-refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1.
Page 417: Figure 12.30 Self-Refresh Timing
Self-refresh timing is shown in figure 12.30. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared.
Page 418 Section 12 Bus State Controller (BSC) Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired.
Page 419: Figure 12.31 Low-Frequency Mode Access Timing
CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.31 Low-Frequency Mode Access Timing Power-Down Mode: If the PDOWN bit in the SDCR register is set to 1, the SDRAM is placed in the power-down mode by bringing the CKE signal to the low level in the non-access cycle.
Page 420: Figure 12.32 Power-Down Mode Access Timing
Section 12 Bus State Controller (BSC) Power-down CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.32 Power-Down Mode Access Timing The conditions to shift to the power-down mode are as follows.
Page 421: Table 12.15 Access Address In Sdram Mode Register Write
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL, and RD/WR signals.
Page 422 Section 12 Bus State Controller (BSC) • Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width CAS Latency 16 bits 32 bits Burst read/burst write (burst length 1): Data Bus Width CAS Latency 16 bits 32 bits Mode register setting timing is shown in figure 12.33.
Page 423: Figure 12.33 Synchronous Dram Mode Write Timing (Based On Jedec)
PALL CKIO A25 to A0 A12/A11* RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 DACKn* Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.33 Synchronous DRAM Mode Write Timing (Based on JEDEC) Low-Power SDRAM: The low-power SDRAM can be accessed using the same protocol as the normal SDRAM.
Page 424: Figure 12.34 Emrs Command Issue Timing
Section 12 Bus State Controller (BSC) Table 12.16 Output Addresses when EMRS Command Is Issued Command to be Access Issued Address CS2 MRS H'A4FD4XX0 CS3 MRS H'A4FD5XX0 CS2 MRS + EMRS H'A4FD4XX0 (with refresh) CS3 MRS + EMRS H'A4FD5XX0 (with refresh) CS2 MRS + EMRS H'A4FD4XX0 (without refresh)
Page 425: Figure 12.35 Deep Power-Down Mode Transition Timing
• Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas.
Page 426: Burst Rom (Clock Asynchronous) Interface
Section 12 Bus State Controller (BSC) 12.5.7 Burst ROM (Clock Asynchronous) Interface The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the address, without negating the RD signal at the end of the 1st cycle.
Page 427: Byte-Selection Sram Interface
CKIO A25 to A0 RD/WR D15 to D0 WAIT DACKn* Note: * The waveform for DACKn when active low is specified. Figure 12.36 Burst ROM Access Timing (Clock Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Accesses = 1) 12.5.8 Byte-Selection SRAM Interface...
Page 428: Figure 12.37 Byte-Selection Ram Basic Access Timing (Bas = 0)
Section 12 Bus State Controller (BSC) CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR Write D31 to D0 DACKn* Figure 12.37 Byte-Selection RAM Basic Access Timing (BAS = 0) Rev. 4.00 Sep. 14, 2005 Page 378 of 982 REJ09B0023-0400 High Note: * The waveform for DACKn is when active low is specified.
Page 429: Figure 12.38 Byte-Selection Ram Basic Access Timing (Bas = 1)
CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR Write D31 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.38 Byte-Selection RAM Basic Access Timing (BAS = 1) Section 12 Bus State Controller (BSC) High Rev.
Page 430: Figure 12.39 Byte-Selection Sram Wait Timing (Bas = 1) (Sw[1:0] = 01, Wr[3:0] = 0001, Hw[1:0] = 01)
Section 12 Bus State Controller (BSC) CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR Write D31 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) Rev.
Page 431: Figure 12.40 Example Of Connection With 32-Bit Data-Width Byte-Selection Sram
This LSI RD/WR Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM This LSI RD/WR Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 381 of 982 64k ×...
Page 432: Burst Mpx-I/O Interface
Section 12 Bus State Controller (BSC) 12.5.9 Burst MPX-I/O Interface Figure 12.42 shows an example of a connection between the LSI and an MPX device. Figures 12.43 to 12.46 show the burst MPX space access timings. Area 6 can be specified as the address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to TYPE0 bits in the CS6BCR register.
Page 433: Figure 12.43 Burst Mpx Space Access Timing (Single Read, No Wait, Or Software Wait 1)
Section 12 Bus State Controller (BSC) Tmd1w Tmd1 CKIO FRAME D31 to D0 A25 to A0 CS6B RD/WR WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.43 Burst MPX Space Access Timing (Single Read, No Wait, or Software Wait 1) Rev.
Page 434: Figure 12.44 Burst Mpx Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1)
Section 12 Bus State Controller (BSC) Tmd1w Tmd1w Tmd1 CKIO FRAME D31 to D0 A25 to A0 CS6B RD/WR WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.44 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1) Rev.
Page 435: Figure 12.45 Burst Mpx Space Access Timing (Burst Read, No Wait, Or Software Wait 1, Cs6Bwcr.mpxmd = 0)
Section 12 Bus State Controller (BSC) Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO FRAME D31 to D0 A25 to A0 CS6B RD/WR WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.45 Burst MPX Space Access Timing (Burst Read, No Wait, or Software Wait 1, CS6BWCR.MPXMD = 0) Rev.
Page 436: Burst Rom Interface (Clock Synchronous)
Section 12 Bus State Controller (BSC) Tmd1 Tmd2 Tmd3 Tmd4 CKIO FRAME D31 to D0 A25 to A0 CS6B RD/WR WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 12.46 Burst MPX Space Access Timing (Burst Write, No Wait, CS6BWCR.MPXMD = 0) 12.5.10 Burst ROM Interface (Clock Synchronous) The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous...
Page 437: 12.5.11 Wait Between Access Cycles
The burst ROM interface performs burst operations for all read accesses. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed.
Page 438 Section 12 Bus State Controller (BSC) 6. Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) For details, see the description of the DMAIWA bit in the CMNCR register. 7.
Page 439: Table 12.18 Minimum Number Of Idle Cycles Between Cpu Access Cycles For The Normal Space Interface
Tables 12.18 to 12.22 lists the minimum number of idle cycles to be inserted for the normal space interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS. Table 12.18 Minimum Number of Idle Cycles between CPU Access Cycles for the Normal Space Interface When Access Size is Less than...
Page 440: Table 12.19 Minimum Number Of Idle Cycles Between Access Cycles During Dmac Dual Address Mode Transfer For The Normal Space Interface
Section 12 Bus State Controller (BSC) Table 12.19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Address Mode Transfer for the Normal Space Interface When Access Size is BSC Register Setting Less than Bus Width CSnWCR. CSnBCR Read to WM Setting Idle Setting...
Page 441: Table 12.20 Minimum Number Of Idle Cycles During Dmac Single Address Mode Transfer To The Normal Space Interface From The External Device With Dack
Table 12.20 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer to the Normal Space Interface from the External Device with DACK (1) Transfer from the external device with DACK to the normal space interface BSC Register Setting* CSnWCR.WM CMNCR.DMAIWA Setting...
Page 442 Section 12 Bus State Controller (BSC) (2) Transfer from the normal space interface to the external device with DACK BSC Register Setting* CSnWCR.WM Setting CSnBCR Idle Setting 0, 1 n (n≥6) Notes: DMAC is operated by Bφ. The minimum number of idle cycles is not affected by changing a clock ratio.
Page 443: Table 12.21 Minimum Number Of Idle Cycles Between Access Cycles Of Cpu And The Dmac Dual Address Mode For The Sdram Interface
Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC Dual Address Mode for the SDRAM Interface BSC Register Setting CSnBCR CS3WCR. CS3WCR. Idle WTRP TRWL Setting Setting Setting CPU Access Read to Write to Read to Read Write...
Page 444 Section 12 Bus State Controller (BSC) BSC Register Setting CSnBCR CS3WCR. CS3WCR. Idle WTRP TRWL Setting Setting Setting Rev. 4.00 Sep. 14, 2005 Page 394 of 982 REJ09B0023-0400 CPU Access Read to Write to Read to Read Write Write 3/3/3/3 5/5/5/5 3/3/4/5 4/4/4/4...
Page 445 BSC Register Setting CSnBCR CS3WCR. CS3WCR. Idle WTRP TRWL Setting Setting Setting n (n>=6)   Notes: The minimum number of idle cycles in CPU Access is described sequentially for Iφ:Bφ (4:1/3:1/2:1/1:1). 1. DMAC is operated by Bφ. The minimum number of idle cycles is not affected by changing a clock ratio.
Page 446: Table 12.22 Minimum Number Of Idle Cycles Between Access Cycles Of The Dmac Single Address Mode For The Sdram Interface
Section 12 Bus State Controller (BSC) Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface (1) Transfer from the external device with DACK to the SDRAM interface BSC Register Setting* CMNCR.DMAIW CS3WCR.WTRP Setting...
Page 447 BSC Register Setting* CMNCR.DMAIW CS3WCR.WTRP Setting Setting  n (n>=6) Section 12 Bus State Controller (BSC) CS3WCR.TRWL Minimum Number of Setting Idle Cycles  Rev. 4.00 Sep. 14, 2005 Page 397 of 982 REJ09B0023-0400...
Page 448 Section 12 Bus State Controller (BSC) (2) Transfer from the SDRAM interface to the external device with DACK BSC Register Setting* CS3BCR Idle Setting n (n>=6) Notes: DMAC is operated by Bφ. The minimum number of idle cycles is not affected by changing a clock ratio.
Page 449: 12.5.12 Bus Arbitration
12.5.12 Bus Arbitration The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus mastership after receiving a bus request from another device. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed.
Page 450: Figure 12.48 Bus Arbitration Timing (Clock Mode 7 Or Cmncr.hizcnt = 1)
Section 12 Bus State Controller (BSC) The sequence for reclaiming the bus mastership from an external device is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. The bus enable signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven.
Page 451: 12.5.13 Others
Section 12 Bus State Controller (BSC) 12.5.13 Others Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. When a power-on reset occurs, internal clocks are synchronized by the reset, then all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized.
Page 452 Section 12 Bus State Controller (BSC) If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus.
Page 453 Section 12 Bus State Controller (BSC) DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. If BSC registers are modified while the write buffer is functioning, correct access cannot be performed.
Page 454 Section 12 Bus State Controller (BSC) Rev. 4.00 Sep. 14, 2005 Page 404 of 982 REJ09B0023-0400...
Page 455: Section 13 Direct Memory Access Controller (Dmac)
Section 13 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.
Page 456: Figure 13.1 Block Diagram Of The Dmac
Section 13 Direct Memory Access Controller (DMAC) • Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. Figure 13.1 shows the block diagram of the DMAC. X/Y memory On-chip peripheral module DMA transfer request signal DMA transfer acknowledge signal Interrupt controller External ROM...
Page 457: Input/Output Pins
13.2 Input/Output Pins The external pins for DMAC are described below. Table 13.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for 2 channels (channels 0 and 1) for external bus use. Table 13.1 Pin Configuration Channel Name DMA transfer request DMA transfer request...
Page 458: Register Descriptions
Section 13 Direct Memory Access Controller (DMAC) 13.3 Register Descriptions Register configuration is described below. See section 24, List of Registers, for the addresses of these registers and the state of them in each processing status. Channel 0: • DMA source address register_0 (SAR_0) •...
Page 459: Dma Source Address Registers (Sar)
13.3.1 DMA Source Address Registers (SAR) DMA source address registers (SAR) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in the single address mode, the SAR is ignored.
Page 460: Dma Channel Control Registers (Chcr)
Section 13 Direct Memory Access Controller (DMAC) 13.3.4 DMA Channel Control Registers (CHCR) DMA channel control registers (CHCR) are 32-bit read/write registers that control the DMA transfer mode. The CHCR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode.
Page 461 Initial Bit Name Value  21 to 18 All 0 Section 13 Direct Memory Access Controller (DMAC) Descriptions Reserved These bits are always read as 0. The write value should always be 0. Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode.
Page 462 Section 13 Direct Memory Access Controller (DMAC) Initial Bit Name Value Rev. 4.00 Sep. 14, 2005 Page 412 of 982 REJ09B0023-0400 Descriptions Source Address Mode SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.)
Page 463 Initial Bit Name Value Section 13 Direct Memory Access Controller (DMAC) Descriptions DREQ Level and DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0 and CHCR_1. These bits are always read as 0 in CHCR_2 and CHCR_3.
Page 464 Section 13 Direct Memory Access Controller (DMAC) Initial Bit Name Value Rev. 4.00 Sep. 14, 2005 Page 414 of 982 REJ09B0023-0400 Descriptions Interrupt Enable This bit specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1.
Page 465 Initial Bit Name Value Note: Writing 0 is possible to clear the flag. Section 13 Direct Memory Access Controller (DMAC) Descriptions DMA Enable This bit enabler or disables the DMA transfer. In an auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1.
Page 466: Dma Operation Register (Dmaor)
Section 13 Direct Memory Access Controller (DMAC) 13.3.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 32-bit read/write register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. The DMAOR is initialized to H'00000000 at reset and retains the current value in the standby or module standby mode.
Page 467 Initial Bit Name Value  23 to 19 All 0 NMIF Section 13 Direct Memory Access Controller (DMAC) Description Priority Mode 1, 0 PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 >...
Page 468 Section 13 Direct Memory Access Controller (DMAC) Initial Bit Name Value  15 to 6 All 0  1, 0 All 0 Note: Writing 0 is possible to clear the flag. If DMA transfers are requested to multiple channels simultaneously, the DMAC performs transfers according to the specified channel priority.
Page 469 Section 13 Direct Memory Access Controller (DMAC) If (PR1 and PR0) = (B'10) is specified, the channel priority is determined according to the settings of the round-robin select bits. In this case, the channel priority is changed between channels whose corresponding round-robin select bit is set to 1. If (PR1 and PR0) = (B'01) is specified, the channel priority is specified as fixed mode 2 (CH0 >...
Page 470: Table 13.2 Combination Of The Round-Robin Select Bits And Priority Mode Bits
Section 13 Direct Memory Access Controller (DMAC) Table 13.2 Combination of the Round-Robin Select Bits and Priority Mode Bits Round-robin Select bit Mode No. — Other than the above setting prohibited (All-channel round-robin) 6 (Fixed mode 2) 7 (Fixed mode 1) Note: * Rev.
Page 471: Dma Extension Resource Selector 0 And 1 (Dmars0, Dmars1)
13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1) DMARS is a 16-bit read/write register that specifies the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3. This register can set the transfer request of SCIF0, SCIF1, SCIF2, MTU0, MTU1, MTU2, MTU3, MTU4, MTU, USB, A/D converter 1, and CMT1.
Page 472 Section 13 Direct Memory Access Controller (DMAC) • DMARS1 Initial Bit Name Value C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 Rev. 4.00 Sep. 14, 2005 Page 422 of 982 REJ09B0023-0400 Description Transfer request module ID for DMA channel 3 (MID).
Page 473: Table 13.3 Transfer Request Module/Register Id
Transfer requests from the various modules are specified by the MID and RID as shown in table 13.3. Table 13.3 Transfer Request Module/Register ID Setting Value for One Peripheral Module Channel (MID + RID) SCIF0 H'88 H'89 SCIF1 H'90 H'91 SCIF2 H'40 H'41...
Page 474: Operation
Section 13 Direct Memory Access Controller (DMAC) 13.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip module request.
Page 475: Figure 13.2 Dma Transfer Flowchart
Figure 13.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Transfer request occurs?* Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated DMATCR = 0? TE = 1...
Page 476: Dma Transfer Requests
Section 13 Direct Memory Access Controller (DMAC) 13.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination.
Page 477: Table 13.5 Selecting External Request Detection With Dl, Ds Bits
Table 13.5 Selecting External Request Detection with Dl, DS Bits CHCR When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK.
Page 478: Table 13.7 Selecting On-Chip Peripheral Module Request Modes With The Rs3 To Rs0 Bits
Section 13 Direct Memory Access Controller (DMAC) On-Chip Peripheral Module Request: In this mode, the transfer is performed in response to the DMA transfer request signal of an on-chip peripheral module. Signals that request DMA transfer include A/D conversion-completed transfer requests from A/D converter 0, compare-match transfer requests from the CMT0 timer, transmit-data empty transfer requests and receive-data full transfer requests from the SCIF0 to SCIF2 that are set by DMARS0 and 1, compare-match and input-capture interrupts from the MTU0 to MTU4 timers, transmit-data-empty transfer requests...
Page 479: Channel Priority
CHCR DMARS Transfer Request RS[3:0] MID Source 1000 101010 00 MTU0 110000 00 MTU1 110010 00 MTU2 110100 00 MTU3 111010 00 MTU4 101000 00 USB transmitter EP2FIFO empty transfer receiver 101100 00 A/D converter 1 ADI (A/D conversion 111100 00 CMT1 13.4.3 Channel Priority...
Page 480: Figure 13.3 Round-Robin Mode
Section 13 Direct Memory Access Controller (DMAC) These are selected by the PR1 and the PR0 bits in the DMA operation register (DMAOR). Round-Robin Mode: Each time one word, byte, or longword is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order.
Page 481: Figure 13.4 Changes In Channel Priority In Round-Robin Mode
Figure 13.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2.
Page 482: Dma Transfer Types
Section 13 Direct Memory Access Controller (DMAC) 13.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode.
Page 483: Figure 13.5 Data Flow Of Dual Address Mode
Address Modes: 1. Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selected) by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle.
Page 484: Figure 13.6 Example Of Dma Transfer Timing In Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
Section 13 Direct Memory Access Controller (DMAC) Figure 13.6 shows an example of DMA transfer timing in dual address mode. CKIO A25 to A0 D31 to D0 DACKn (Active-Low) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn.
Page 485: Figure 13.7 Data Flow In Single Address Mode
This LSI DMAC Data flow Figure 13.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory.
Page 486: Figure 13.8 Example Of Dma Transfer Timing In Single Address Mode
Section 13 Direct Memory Access Controller (DMAC) Figure 13.8 shows example of DMA transfer timing in single address mode. A25 to A0 D31 to D0 DACKn (a) External device with DACK → external memory space (ordinary memory) A25 to A0 D31 to D0 DACKn (b) External memory space (ordinary memory) →...
Page 487: Figure 13.9 Dma Transfer Example In The Cycle-Steal Normal Mode (Dual Address, Dreq Low Level Detection)
Figure 13.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level detection DREQ Bus cycle Figure 13.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) •...
Page 488: Figure 13.10 Example Of Dma Transfer In Cycle Steal Intermittent Mode (Dual Address, Dreq Low Level Detection)
Section 13 Direct Memory Access Controller (DMAC) DREQ Bus cycle Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) 2. Burst Mode Once the bus mastership is obtained, the transfer is performed continuously until the transfer end condition is satisfied.
Page 489: Table 13.9 Relationship Of Request Modes And Bus Modes By Dma Transfer Category
Table 13.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category External device with DACK and external memory Dual External device with DACK and memory-mapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memory- mapped external device...
Page 490: Number Of Bus Cycle States And Dreq Pin Sampling Timing
Section 13 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority Order: When channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately.
Page 491: Figure 13.13 Example Of Dreq Input Detection In Cycle Steal Mode Edge Detection
CKIO Bus cycle DREQ (Rising) DACK (Active-high) Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Rising) DACK (Active-high) CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection CKIO Bus cycle DREQ...
Page 492: Figure 13.16 Example Of Dreq Input Detection In Burst Mode Level Detection
Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising) DACK (Active-high) CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection Figure 13.17 shows the TEND output timing. CKIO Bus cycle DREQ...
Page 493: Figure 13.18 Bsc Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access To 16-Bit Device)
To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in figure 13.18. Address Read D15 to D0 Write D15 to D0...
Page 494: Completion Of Dma Transfer
Section 13 Direct Memory Access Controller (DMAC) 13.4.6 Completion of DMA Transfer The conditions for the completion of DMA transfer differ according to whether we are considering completion of transfer on individual channels or simultaneous completion of transfer on all channels.
Page 495: Notes On Usage
• When an address error occurs during a read cycle: Neither read cycles nor write cycles are generated; only the transfer request is cleared. However, when the transfer-request source was an on-chip peripheral module (MTU), use whichever of the following methods is appropriate to clear the transfer request. a.
Page 496: Notes On Dreq Sampling When Dack Is Divided In External Access
Section 13 Direct Memory Access Controller (DMAC) 6. Note the followings when the DMA transfer request is sent from the SCIF. Even when the DMAC has completed the TCR times of transfers (the TE bit in CHCR = 1), the DMAC accepts and keeps the transfer request from the SCIF (max. one time of transfer) if all the conditions shown below are satisfied.
Page 497: Figure 13.19 Example Of Dreq Input Detection In Cycle Steal Mode Edge Detection When Dack Is Divided To 4 By Idle Cycles
• Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more) • External wait mask specification (WM = 0). In addition to the above conditions, the following conditions are included depending on the detection method of DREQ. •...
Page 498: Figure 13.21 Example Of Dreq Input Detection In Cycle Steal Mode Level Detection When Dack Is Divided To 4 By Idle Cycles
Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle 1st acceptance DREQ (Overrun 0, Non-sensitive period high-level) DACK (High-active) CKIO Bus cycle 1st acceptance DREQ (Overrun 1, high-level) Non-sensitive period DACK (High-active) Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 4 by Idle Cycles Rev.
Page 499: Figure 13.22 Example Of Dreq Input Detection In Cycle Steal Mode Level Detection When Dack Is Divided To 2 By Idle Cycles
CKIO Bus cycle DREQ (Overrun 0, high-level) DACK (High-active) CKIO Bus cycle DREQ (Overrun 1, high-level) DACK (High-active) Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 2 by Idle Cycles Notes For the external access described in (2) above, note the following.
Page 500 Section 13 Direct Memory Access Controller (DMAC) Rev. 4.00 Sep. 14, 2005 Page 450 of 982 REJ09B0023-0400...
Page 501: Section 14 U Memory
This LSI has on-chip U memory. It can be used by the CPU, DSP, and DMAC to store instructions or data. 14.1 Features The U memory features are listed in table 14.1. Table 14.1 U Memory Specifications Parameter Features Addressing method Mapping is possible in space P0 or P2 Ports 2 independent read/write ports...
Page 502: U Memory Access From Cpu
Section 14 U Memory 14.2 U Memory Access from CPU The U memory can be accessed by the CPU from spaces P0 and P2. Access from the CPU is via the I bus when U memory is space P0, and via the L bus when space P2. To use the L bus, one cycle access is performed unless page conflict occurs.
Page 503: Usage Note
14.5 Usage Note When accessing the U memory by the CPU or the DSP, if the cache is on, access must be performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be guaranteed. When the cache is off, spaces P0 and P2 can both be used. 14.6 Sleep Mode In sleep mode, the U memory cannot be accessed by the I bus master module such as DMAC.
Page 504 Section 14 U Memory Rev. 4.00 Sep. 14, 2005 Page 454 of 982 REJ09B0023-0400...
Page 505: Section 15 User Debugging Interface (H-Udi)
Section 15 User Debugging Interface (H-UDI) This LSI incorporates a user debugging interface (H-UDI) and advanced user debugger (AUD) for a boundary scan function and emulator support. This section describes the H-UDI. The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD.
Page 506: Input/Output Pins
Section 15 User Debugging Interface (H-UDI) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the H-UDI. Table 15.1 Pin Configuration Pin Name Input/Output Input Input TRST Input Input Output ASEMD0* Input ASEBRKAK, Output AUDSYNC, AUDATA3 to AUDATA 0, AUDCK Note: When the emulator is not in use, fix this pin to the high level.
Page 507: Register Descriptions
15.3 Register Descriptions The H-UDI has the following registers. Refer the section 24, List of Registers, for the addresses and access size for these registers. • Bypass register (SDBPR) • Instruction register (SDIR) • Boundary scan register (SDBSR) • ID register (SDID) 15.3.1 Bypass Register (SDBPR) SDBPR is a 1-bit register that cannot be accessed by the CPU.
Page 508: Boundary Scan Register (Sdbsr)
Section 15 User Debugging Interface (H-UDI) Table 15.2 H-UDI Commands Bits 15 to 8 — Other than the above 15.3.3 Boundary Scan Register (SDBSR) SDBSR is a 469-bit shift register, located on the PAD, for controlling the input/output pins of this LSI.
Page 509: Table 15.3 This Lsi Pins And Boundary Scan Register Bits
Table 15.3 This LSI Pins and Boundary Scan Register Bits Pin Name From TDI CS3/PTA3 CS2/PTA2 UCLK/PTB0 VBUS/PTB1 SUSPND/PTB2 XVDATA/PTB3 TXENL/PTB4 TXDMNS/PTB5 TXDPLS/PTB6 DMNS/PTB7 DPLS/PTB8 A19/PTA8 A20/PTA9 A21/PTA10 A22/PTA11 A23/PTA12 A24/PTA13 A25/PTA14 AUDATA0/PTJ8 AUDATA1/PTJ9 AUDATA2/PTJ10 Section 15 User Debugging Interface (H-UDI) Pin Name AUDATA3/PTJ11 AUDSYNC/PTJ12...
Page 510 Section 15 User Debugging Interface (H-UDI) Pin Name DPLS/PTB8 A19/PTA8 A20/PTA9 A21/PTA10 A22/PTA11 A23/PTA12 A24/PTA13 AUDCK A25/PTA14 AUDATA0/PTJ8 AUDATA1/PTJ9 AUDATA2/PTJ10 AUDATA3/PTJ11 AUDSYNC/PTJ12 IRQ0/PTJ0 IRQ1/PTJ1 IRQ2/PTJ2 IRQ3/PTJ3 IRQ4/PTJ4 IRQ5/PTJ5 IRQ6/PTJ6 IRQ7/PTJ7 SCK0/PTH0 Rev. 4.00 Sep. 14, 2005 Page 460 of 982 REJ09B0023-0400 Pin Name CS3/PTA3...
Page 511 Pin Name IRQ7/PTJ7 SCK0/PTH0 CTS0/PTH1 TxD0/PTH2 RxD0/PTH3 RTS0/PTH4 SCK1/PTH5 CTS1/PTH6 TxD1/PTH7 RxD1/PTH8 RTS1/PTH9 SCK2/PTH10 CTS2/PTH11 TxD2/PTH12 RxD2/PTH13 RTS2/PTH14 TIOC4D/PTE0 TIOC4C/PTE1 TIOC4B/PTE2 TIOC4A/PTE3 TIOC3D/PTE4 TIOC3B/PTE6 TIOC3C/PTE5 TIOC3A/PTE7 TIOC2B/PTE8 TIOC2A/PTE9 TIOC1B/PTE10 TIOC1A/PTE11 TIOC0D/PTE12 TIOC0C/PTE13 TIOC0B/PTE14 TIOC0A/PTE15 Section 15 User Debugging Interface (H-UDI) Pin Name Control TCLKD/PTF8...
Page 512 Section 15 User Debugging Interface (H-UDI) Pin Name CTS2/PTH11 TxD2/PTH12 RxD2/PTH13 RTS2/PTH14 TIOC4D/PTE0 TIOC4C/PTE1 TIOC4B/PTE2 TIOC4A/PTE3 TIOC3D/PTE4 TIOC3B/PTE6 TIOC3C/PTE5 TIOC3A/PTE7 TIOC2B/PTE8 TIOC2A/PTE9 TIOC1B/PTE10 TIOC1A/PTE11 TIOC0D/PTE12 TIOC0C/PTE13 TIOC0B/PTE14 TIOC0A/PTE15 TCLKD/PTF8 TCLKC/PTF9 TCLKB/PTF10 TCLKA/PTF11 POE0/PTF12 POE1/PTF13 POE2/PTF14 POE3/PTF15 PTF0 PTF1 PTF2 PTF3 Rev.
Page 513 Pin Name TIOC2B/PTE8 TIOC2A/PTE9 TIOC1B/PTE10 TIOC1A/PTE11 TIOC0D/PTE12 TIOC0C/PTE13 TIOC0B/PTE14 TIOC0A/PTE15 TCLKD/PTF8 TCLKC/PTF9 TCLKB/PTF10 TCLKA/PTF11 POE0/PTF12 POE1/PTF13 POE2/PTF14 POE3/PTF15 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 PTF7 PTG8 PTG9/SCL PTG10/SDA PTG11 PTG12 PTG13 AN0/PTG0 AN1/PTG1 Section 15 User Debugging Interface (H-UDI) Pin Name Control AN2/PTG2...
Page 514 Section 15 User Debugging Interface (H-UDI) Pin Name D28/PTD12 D27/PTD11 D26/PTD10 DREQ0/PTC9 DREQ1/PTC10 STATUS0/PTC14 STATUS1/PTC15 BREQ/PTC6 BACK/PTC7 ASEBRKAK/PTC13 CS6B/PTC4 CS6A/PTC3 CS5B/PTC2 CS5A/PTC1 CS4/PTC0 TEND/PTC8 FRAME/PTC5 DACK0/PTC11 DACK1/PTC12 D31/PTD15 D30/PTD14 D29/PTD13 D28/PTD12 D27/PTD11 D26/PTD10 DREQ0/PTC9 DREQ1/PTC10 STATUS0/PTC14 STATUS1/PTC15 Rev. 4.00 Sep. 14, 2005 Page 464 of 982 REJ09B0023-0400 Pin Name BREQ/PTC6...
Page 515 Pin Name RASU/PTA7 CKE/PTA1 CASL/PTA4 RASL/PTA6 A0/PTA0 D25/PTD9 D24/PTD8 D23/PTD7 D22/PTD6 D21/PTD5 D20/PTD4 D19/PTD3 D18/PTD2 D17/PTD1 D16/PTD0 RDWR WE0/DQMLL WE1/DQMLU CASU/PTA5 WE3/DQMUU/AH RASU/PTA7 WE2/DQMUL CKE/PTA1 CASL/PTA4 Section 15 User Debugging Interface (H-UDI) Pin Name RASL/PTA6 A0/PTA0 D25/PTD9 D24/PTD8 D23/PTD7 D22/PTD6 D21/PTD5 Rev.
Page 516 Section 15 User Debugging Interface (H-UDI) Pin Name D20/PTD4 D19/PTD3 D18/PTD2 D17/PTD1 D16/PTD0 RD/WR WE0/DQMLL WE1/DQMLU CASU/PTA5 WE3/DQMUU/AH RASU/PTA7 WE2/DQMUL CKE/PTA1 CASL/PTA4 RASL/PTA6 Notes: 1. Control is an active-high signal. 2. When Control is driven high, the corresponding pin is driven by the value of OUT. 3.
Page 517: Id Register (Sdid)
15.3.4 ID Register (SDID) The ID register (SDID) is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by CPU. The IDCODE command is set from the H-UDI pin. This register can be read from the TDO when the TAP state is Shift-DR.
Page 518: Operation
Section 15 User Debugging Interface (H-UDI) 15.4 Operation 15.4.1 TAP Controller Figure 15.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. Test-logic-reset Run-test/idle Figure 15.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK;...
Page 519: Reset Configuration
15.4.2 Reset Configuration Table 15.4 Reset Configuration ASEMD0* RESETP Notes: 1. Performs normal mode and ASE mode settings ASEMD0 = H, normal mode ASEMD0 = L, ASE mode 2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RESETP pin is negated.
Page 520: H-Udi Reset
Section 15 User Debugging Interface (H-UDI) (when the H-UDI command is set) (when the boundary scan command is set) Figure 15.3 H-UDI Data Transfer Timing 15.4.4 H-UDI Reset An H-UDI reset is executed by inputting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset.
Page 521: Boundary Scan
15.5 Boundary Scan A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode stipulated by JTAG. 15.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and HIGHZ).
Page 522: Points For Attention
Section 15 User Debugging Interface (H-UDI) EXTEST: This instruction is provided to test external circuitry when the this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board.
Page 523: Section 16 I C Bus Interface 2 (Iic2)
Section 16 I The I C bus interface 2 conforms to and provides a subset of the Philips I interface functions. However, the configuration of the registers that control the I partly from the Philips register configuration. Figure 16.1 shows a block diagram of the I I/O pin connections to external circuits.
Page 524: C Bus Interface
Section 16 I C Bus Interface 2 (IIC2) Output control Noise canceler Output control Noise canceler [Legend] ICCR1 : C bus control register 1 ICCR2 : C bus control register 2 C bus mode register ICMR : ICSR : C bus status register ICIER : C bus interrupt enable register ICDRT :...
Page 525: Input/Output Pins
SCL in SCL out SDA in SDA out (Master) Note: * The I C bus power supply and this LSI's power supply (VccQ) must be switched ON or OFF simultaneously. Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 shows the pin configuration for the I Table 16.1 I C Bus Interface Pin Configuration...
Page 526: Register Descriptions
Section 16 I C Bus Interface 2 (IIC2) 16.3 Register Descriptions The I C bus interface 2 has the following registers: • I C bus control register 1 (ICCR1) • I C bus control register 2 (ICCR2) • I C bus mode register (ICMR) •...
Page 527 Initial Bit Name Value CKS3 CKS2 CKS1 CKS0 Description Master/Slave Select Transmit/Receive Select In master mode with the I arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
Page 528: Table 16.2 Transfer Rate
Section 16 I C Bus Interface 2 (IIC2) Table 16.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Note: Set the value that satisfies the external specifications. Rev. 4.00 Sep. 14, 2005 Page 478 of 982 REJ09B0023-0400 φ=5 MHz φ=10 MHz...
Page 529: C Bus Control Register 2 (Iccr2)
16.3.2 C Bus Control Register 2 (ICCR2) ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I Initial Bit Name Value BBSY SDAO Description Bus Busy...
Page 530: C Bus Mode Register (Icmr)
Section 16 I C Bus Interface 2 (IIC2) Initial Bit Name Value SDAOP SCLO  IICRST  16.3.3 C Bus Mode Register (ICMR) ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. ICMR is initialized to H'38 by a power-on reset.
Page 531 Initial Bit Name Value  5, 4 All 1 BCWP Description  Reserved These bits are always read as 1. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0. In clock synchronous serial mode, BC should not be modified.
Page 532: C Bus Interrupt Enable Register (Icier)
Section 16 I C Bus Interface 2 (IIC2) 16.3.4 C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits received.
Page 533 Initial Bit Name Value STIE ACKE ACKBR ACKBT Description Stop Condition Detection Interrupt Enable This bit enables or disables the stop condition (STPI) when the STOP bit in ICSR is set . 0: Stop condition detection interrupt request (STPI) is disabled.
Page 534: C Bus Status Register (Icsr)
Section 16 I C Bus Interface 2 (IIC2) 16.3.5 C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status. ICSR is initialized to H'00 by a power-on reset. Initial Bit Name Value TDRE TEND...
Page 535 Initial Bit Name Value NACKF STOP AL/OVE Description No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • When 0 is written in NACKF after reading NACKF Stop Condition Detection Flag [Setting condition] •...
Page 536: Slave Address Register (Sar)
Section 16 I C Bus Interface 2 (IIC2) Initial Bit Name Value 16.3.6 Slave Address Register (SAR) SAR is an 8-bit readable/writable register that selects the communications format and sets the slave address. In slave mode with the I upper seven bits of the first frame received after a start condition, this module operates as the slave device.
Page 537: C Bus Transmit Data Register (Icdrt)
16.3.7 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
Page 538: Operation
Section 16 I C Bus Interface 2 (IIC2) 16.4 Operation The I C bus interface can communicate either in I by setting FS in SAR. 16.4.1 C Bus Format Figure 16.3 shows the I C bus formats. Figure 16.4 shows the I following a start condition always consists of eight bits.
Page 539: Master Transmit Operation
[Legend] Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge.
Page 540: Figure 16.5 Master Transmit Mode Operation Timing (1)
Section 16 I C Bus Interface 2 (IIC2) (Master output) Bit 7 Bit 6 (Master output) (Slave output) TDRE TEND ICDRT ICDRS User [2] Instruction of start processing condition issuance [3] Write data to ICDRT (first byte) Figure 16.5 Master Transmit Mode Operation Timing (1) (Master output) Bit 7 (Master output)
Page 541: Master Receive Operation
16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown below.
Page 542: Figure 16.7 Master Receive Mode Operation Timing (1)
Section 16 I C Bus Interface 2 (IIC2) Master transmit mode (Master output) (Master output) (Slave output) TDRE TEND RDRF ICDRS ICDRR User processing [1] Clear TDRE after clearing TEND and TRS Figure 16.7 Master Receive Mode Operation Timing (1) Rev.
Page 543: Slave Transmit Operation
(Master output) (Master output) Bit 7 (Slave output) RDRF RCVD ICDRS Data n-1 ICDRR Data n-1 User [5] Read ICDRR after setting RCVD processing Figure 16.8 Master Receive Mode Operation Timing (2) 16.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal.
Page 544: Figure 16.9 Slave Transmit Mode Operation Timing (1)
Section 16 I C Bus Interface 2 (IIC2) 5. Clear TDRE. Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) (Slave output) TDRE TEND ICDRT ICDRS ICDRR User [2] Write data to ICDRT (data 1) processing Figure 16.9 Slave Transmit Mode Operation Timing (1) Rev.
Page 545: Figure 16.10 Slave Transmit Mode Operation Timing (2)
(Master output) (Master output) (Slave output) Bit 7 (Slave output) TDRE TEND ICDRT ICDRS ICDRR User processing Figure 16.10 Slave Transmit Mode Operation Timing (2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Data n [3] Clear TEND Section 16 I C Bus Interface 2 (IIC2) Slave receive...
Page 546: Slave Receive Operation
Section 16 I C Bus Interface 2 (IIC2) 16.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 16.11 and 16.12.
Page 547: Clocked Synchronous Serial Format
(Master output) Bit 7 (Master output) (Slave output) (Slave output) RDRF ICDRS ICDRR User processing Figure 16.12 Slave Receive Mode Operation Timing (2) 16.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1.
Page 548: Figure 16.14 Transmit Mode Operation Timing
Section 16 I C Bus Interface 2 (IIC2) Transmit Operation: In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 16.14.
Page 549 Receive Operation: In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 16.15.
Page 550: Figure 16.15 Receive Mode Operation Timing
Section 16 I C Bus Interface 2 (IIC2) Bit 0 (Input) RDRF Data 1 ICDRS ICDRR User [2] Set MST processing (when outputting the clock) Figure 16.15 Receive Mode Operation Timing Bit 0 (Input) RCVD BC2 to BC0 [2] Set MST Figure 16.16 Operation Timing For Receiving One Byte Rev.
Page 551: Noise Filter
16.4.7 Noise Filter The logic levels at the SCL and SDA pins are routed through noise filters before being latched internally. Figure 16.17 shows a block diagram of the noise filter circuit. The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock.
Page 552: Example Of Use
Section 16 I C Bus Interface 2 (IIC2) 16.4.8 Example of Use Flowcharts in respective modes that use the I Start Initialize Read BBSY in ICCR2 BBSY=0 ? Set MST and TRS in ICCR1 to 1 Write 1 to BBSY and 0 to SCP Write transmit data in ICDRT...
Page 553: Figure 16.19 Sample Flowchart For Master Receive Mode
Mater receive mode Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR RDRF=1 ? Last receive - 1? Read ICDRR Set ACKBT in ICIER to 1 Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR...
Page 554: Figure 16.20 Sample Flowchart For Slave Transmit Mode
Section 16 I C Bus Interface 2 (IIC2) Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR TDRE=1 ? Last byte? Write transmit data in ICDRT Read TEND in ICSR TEND=1 ? Clear TEND in ICSR Set TRS in ICCR1 to 0 Dummy-read ICDRR Clear TDRE in ICSR...
Page 555: Figure 16.21 Sample Flowchart For Slave Receive Mode
Slave receive mode Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR RDRF=1 ? Last receive - 1? Read ICDRR Set ACKBT in ICIER to 1 Read ICDRR Read RDRF in ICSR RDRF=1 ? Read ICDRR Figure 16.21 Sample Flowchart for Slave Receive Mode Section 16 I...
Page 556: Interrupt Request
Section 16 I C Bus Interface 2 (IIC2) 16.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 16.3 shows the contents of each interrupt request. Table 16.3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition...
Page 557: Bit Synchronous Circuit
16.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull- up resistance) Therefore, it monitors SCL and communicates by bit with synchronization.
Page 558: Usage Note
Section 16 I C Bus Interface 2 (IIC2) 16.7 Usage Note Start (retransmission) and stop conditions should be generated after the fall of the ninth clock pulse has been detected. To detect the fall of the ninth clock pulse, read the SCLO bit in the I Bus Control Register 2 (ICCR2).
Page 559: Section 17 Compare Match Timer (Cmt)
Section 17 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals. 17.1 Features CMT has the following features. •...
Page 560: Register Descriptions
Section 17 Compare Match Timer (CMT) 17.2 Register Descriptions The CMT has the following registers. Refer the section 24, List of Registers and access size for these registers. • Compare match timer start register_0 (CMSTR_0) • Compare match timer control/status register_0 (CMCSR_0) •...
Page 561: Compare Match Timer Control/Status Register (Cmcsr)
17.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables interrupts or DMA transfer requests, and selects the counter input clock. CMCSR is initialized to H'0000 by a power on reset, but is not initialized in standby mode. Initial Bit Name value...
Page 562: Compare Match Counter (Cmcnt )
Section 17 Compare Match Timer (CMT) Initial Bit Name value CKS1 CKS0 Note: Only 0 can be written, to clear the flag. 17.2.3 Compare Match Counter (CMCNT ) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock.
Page 563: Operation
17.3 Operation 17.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
Page 564: Compare Matches
Section 17 Compare Match Timer (CMT) 17.4 Compare Matches 17.4.1 Timing of Compare Match Flag Setting When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last state in which the values match (when the CMCNT value is updated to H'0000).
Page 565: Timing Of Compare Match Flag Clearing
Section 17 Compare Match Timer (CMT) 17.4.3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. Rev. 4.00 Sep. 14, 2005 Page 515 of 982 REJ09B0023-0400...
Page 566 Section 17 Compare Match Timer (CMT) Rev. 4.00 Sep. 14, 2005 Page 516 of 982 REJ09B0023-0400...
Page 567: Section 18 Multi-Function Timer Pulse Unit (Mtu)
Section 18 Multi-Function Timer Pulse Unit (MTU) This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 18.1. 18.1 Features • Maximum 16-pulse input/output • Selection of 8 counter input clocks for each channel •...
Page 568: Table 18.1 Mtu Functions
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.1 MTU Functions Item Channel 0 φ/1 Count clock φ/4 φ/16 φ/64 TCLKA TCLKB TCLKC TCLKD General registers TGRA_0 TGRB_0 General registers/ TGRC_0 buffer registers TGRD_0 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D Counter clear function compare...
Page 569 Item Channel 0 DMA activation TGRA_0 compare match or input capture A/D converter TGRA_0 start trigger compare match or input capture Interrupt sources 5 sources • Compare match or input capture • Compare match or input capture • Compare match or input capture •...
Page 570: Figure 18.1 Block Diagram Of Mtu
Section 18 Multi-Function Timer Pulse Unit (MTU) Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 Internal clock External clock TCLKA TCLKB TCLKC TCLKD Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D...
Page 571: Input/Output Pins
18.2 Input/Output Pins Table 18.2 MTU Pin Configuration Channel Symbol TCLKA Input TCLKB Input TCLKC Input TCLKD Input TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Section 18 Multi-Function Timer Pulse Unit (MTU) Function External clock A input pin (Channel 1 phase counting mode A phase input)
Page 572: Register Descriptions
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3 Register Descriptions The MTU has the following registers. To distinguish registers in each channel, TCR for channel 0 is expressed as TCR_0. • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) •...
Page 573 Section 18 Multi-Function Timer Pulse Unit (MTU) • Timer I/O control register L_3 (TIORL_3) • Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) •...
Page 574: Timer Control Register (Tcr)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings should be conducted only when TCNT operation is stopped.
Page 575: Table 18.3 Cclr0 To Cclr2 (Channels 0, 3, And 4)
Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4) Bit 7 Bit 6 Channel CCLR2 CCLR1 0, 3, 4 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Page 576: Table 18.5 Tpsc0 To Tpsc2 (Channel 0)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.5 TPSC0 to TPSC2 (Channel 0) Bit 2 Bit 1 Channel TPSC2 TPSC1 Table 18.6 TPSC0 to TPSC2 (Channel 1) Bit 2 Bit 1 Channel TPSC2 TPSC1 Note: This setting is ignored when channel 1 is in phase counting mode. Rev.
Page 577: Table 18.7 Tpsc0 To Tpsc2 (Channel 2)
Table 18.7 TPSC0 to TPSC2 (Channel 2) Bit 2 Bit 1 Channel TPSC2 TPSC1 Note: This setting is ignored when channel 2 is in phase counting mode. Table 18.8 TPSC0 to TPSC2 (Channels 3 and 4) Bit 2 Bit 1 Channel TPSC2 TPSC1...
Page 578: Timer Mode Register (Tmdr)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped.
Page 579: Table 18.9 Md0 To Md3
Table 18.9 MD0 to MD3 Bit 3 Bit 2 Bit 1 Bit 0 [Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3, 4. 2. Phase counting mode cannot be set for channels 0, 3, 4. 3.
Page 580: Timer I/O Control Register (Tior)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting.
Page 581 • TIORL_0, TIORL_3, TIORL_4 Initial Bit Name value IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Section 18 Multi-Function Timer Pulse Unit (MTU) Description I/O Control D3 to D0 Specify the function of TGRD. When TGRD is used as the buffer register of TGRB, this setting is disabled, and input capture/output compare does not occur.
Page 582: Table 18.10 Tiorh_0 (Channel 0)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.10 TIORH_0 (Channel 0) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] X: Don't care Note: * 0 is output until TIOR contents is specified after a power-on reset and entering standby mode.
Page 583: Table 18.11 Tiorl_0 (Channel 0)
Table 18.11 TIORL_0 (Channel 0) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2.
Page 584: Table 18.12 Tior_1 (Channel 1)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.12 TIOR_1 (Channel 1) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 585: Table 18.13 Tior_2 (Channel 2)
Table 18.13 TIOR_2 (Channel 2) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. Section 18 Multi-Function Timer Pulse Unit (MTU) Description TGRB_2...
Page 586: Table 18.14 Tiorh_3 (Channel 3)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.14 TIORH_3 (Channel 3) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 587: Table 18.15 Tiorl_3 (Channel 3)
Table 18.15 TIORL_3 (Channel 3) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2.
Page 588: Table 18.16 Tiorh_4 (Channel 4)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.16 TIORH_4 (Channel 4) Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 589: Table 18.17 Tiorl_4 (Channel 4)
Table 18.17 TIORL_4 (Channel 4) Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2.
Page 590: Table 18.18 Tiorh_0 (Channel 0)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.18 TIORH_0 (Channel 0) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 591: Table 18.19 Tiorl_0 (Channel 0)
Table 18.19 TIORL_0 (Channel 0) Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2.
Page 592: Table 18.20 Tior_1 (Channel 1)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.20 TIOR_1 (Channel 1) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 593: Table 18.21 Tior_2 (Channel 2)
Table 18.21 TIOR_2 (Channel 2) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. Section 18 Multi-Function Timer Pulse Unit (MTU) Description TGRA_2...
Page 594: Table 18.22 Tiorh_3 (Channel 3)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.22 TIORH_3 (Channel 3) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 595: Table 18.23 Tiorl_3 (Channel 3)
Table 18.23 TIORL_3 (Channel 3) Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2.
Page 596: Table 18.24 Tiorh_4 (Channel 4)
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.24 TIORH_4 (Channel 4) Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 [Legend] X: Don't care Note: The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode.
Page 597: Table 18.25 Tiorl_4 (Channel 4)
Table 18.25 TIORL_4 (Channel 4) Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 [Legend] X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset and entering standby mode. 2.
Page 598: Timer Interrupt Enable Register (Tier)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU has five TIER registers, one for each channel. Initial Bit Name value...
Page 599 Initial Bit Name value TGIED TGIEC TGIEB TGIEA Note: Do not change the setting of the timer interrupt enable register (TIER) during DMA transfer. Section 18 Multi-Function Timer Pulse Unit (MTU) Description TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4.
Page 600: Timer Status Register (Tsr)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU has five TSR registers, one for each channel. Initial Bit Name value TCFD ...
Page 601 Initial Bit Name value TCFV TGFD Section 18 Multi-Function Timer Pulse Unit (MTU) Description R/(W) Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting conditions] • When the TCNT value overflows (changes from H'FFFF to H'0000 ) •...
Page 602 Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value TGFC TGFB Rev. 4.00 Sep. 14, 2005 Page 552 of 982 REJ09B0023-0400 Description R/(W) Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing.
Page 603: Timer Counter (Tcnt)
Initial Bit Name value TGFA Note: Write 0 after reading TGFA=1 only when a DMA address error occurs during a DMA read cycle. 18.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one for each channel.
Page 604: Timer Start Register (Tstr)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Page 605 Initial Bit Name value SYNC4 SYNC3  5 to 3 All 0 SYNC2 SYNC1 SYNC0 Section 18 Multi-Function Timer Pulse Unit (MTU) Description Timer Synchro 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another...
Page 606: Timer Output Master Enable Register (Toer)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.10 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set.
Page 607: Timer Output Control Register (Tocr)
18.3.11 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Initial Bit Name value  PSYE  5 to 2 All 0 OLSN...
Page 608: Figure 18.2 Complementary Pwm Mode Output Level Example
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.27 Output Level Select Function Bit 1 OLSP Initial Output Active Level High level Low level Low level High level Figure 18.2 shows an example of complementary PWM mode output (one phase) when OLSN = 1, OLSP = 1.
Page 609: Timer Gate Control Register (Tgcr)
18.3.12 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/reset- synchronized PWM mode.
Page 610: Table 18.28 Output Level Select Function
Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value Table 18.28 Output level Select Function Bit 2 Bit 1 Bit 0 TIOC3B U Phase Rev. 4.00 Sep. 14, 2005 Page 560 of 982 REJ09B0023-0400 Description External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input...
Page 611: Timer Subcounter (Tcnts)
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.13 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. Note: Accessing TCNTS in 8-bit units is prohibited. Always access in 16-bit units. 18.3.14 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values.
Page 612: 18.3.17 Bus Master Interface
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.3.17 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register (TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible.
Page 613: Figure 18.3 Example Of Counter Operation Setting Procedure
Example of Count Operation Setting Procedure: Figure 18.3 shows an example of the count operation setting procedure. Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Start count operation <Periodic counter> Figure 18.3 Example of Counter Operation Setting Procedure Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU's TCNT counters are all designated as free-running counters.
Page 614: Figure 18.4 Free-Running Counter Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT value H'FFFF H'0000 CST bit TCFV Figure 18.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR.
Page 615: Figure 18.6 Example Of Setting Procedure For Waveform Output By Compare Match
Example of Setting Procedure for Waveform Output by Compare Match: Figure 18.6 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode Set output timing Start count operation <Waveform output> Figure 18.6 Example of Setting Procedure for Waveform Output by Compare Match Examples of Waveform Output Operation: Figure 18.7 shows an example of 0 output/1 output.
Page 616: Figure 18.8 Example Of Toggle Output Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
Page 617: Figure 18.9 Example Of Input Capture Operation Setting Procedure
Example of Input Capture Operation Setting Procedure: Figure 18.9 shows an example of the input capture operation setting procedure. Input selection Select input capture input Start count <Input capture operation> Figure 18.9 Example of Input Capture Operation Setting Procedure Example of Input Capture Operation: Figure 18.10 shows an example of input capture operation.
Page 618: Synchronous Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 TIOCA TGRA H'0005 TIOCB TGRB Figure 18.10 Example of Input Capture Operation 18.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting).
Page 619: Figure 18.11 Example Of Synchronous Operation Setting Procedure
Example of Synchronous Operation Setting Procedure: Figure 18.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation Synchronous presetting Set TCNT <Synchronous presetting> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters.
Page 620: Figure 18.12 Example Of Synchronous Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation: Figure 18.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 621: Buffer Operation
18.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 18.29 shows the register combinations used in buffer operation.
Page 622: Figure 18.14 Input Capture Buffer Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 18.14.
Page 623: Figure 18.16 Example Of Buffer Operation (1)
Examples of Buffer Operation: • When TGR is an output compare register Figure 18.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 624: Cascaded Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT value H'0F07 H'09FB H'0532 H'0000 TIOCA TGRA TGRC Figure 18.17 Example of Buffer Operation (2) 18.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
Page 625: Figure 18.18 Cascaded Operation Setting Procedure
Example of Cascaded Operation Setting Procedure: Figure 18.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> Figure 18.18 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 18.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2.
Page 626: Pwm Modes
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Page 627: Table 18.31 Pwm Output Registers And Output Pins
The correspondence between PWM output pins and registers is shown in table 18.31. Table 18.31 PWM Output Registers and Output Pins Channel Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Section 18 Multi-Function Timer Pulse Unit (MTU) Output Pins PWM Mode 1...
Page 628: Figure 18.20 Example Of Pwm Mode Setting Procedure
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of PWM Mode Setting Procedure: Figure 18.20 shows an example of the PWM mode setting procedure. PWM mode Select counter clock Select counter clearing source Select waveform output level Set TGR Set PWM mode Start count <PWM mode>...
Page 629: Figure 18.22 Example Of Pwm Mode Operation (2)
Figure 18.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform.
Page 630: Figure 18.23 Example Of Pwm Mode Operation (3)
Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TIOCA TCNT value TGRB rewritten TGRA TGRB H'0000 TIOCA TCNT value...
Page 631: Phase Counting Mode
18.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR.
Page 632: Figure 18.24 Example Of Phase Counting Mode Setting Procedure
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Phase Counting Mode Setting Procedure: Figure 18.24 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode Start count <Phase counting mode> Figure 18.24 Example of Phase Counting Mode Setting Procedure Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks.
Page 633: Figure 18.26 Example Of Phase Counting Mode 2 Operation
Table 18.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level High level Low level [Legend] : Rising edge : Falling edge • Phase counting mode 2 Figure 18.26 shows an example of phase counting mode 2 operation, and table 18.34 summarizes the TCNT up/down-count conditions.
Page 634: Figure 18.27 Example Of Phase Counting Mode 3 Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level High level Low level [Legend] : Rising edge : Falling edge • Phase counting mode 3 Figure 18.27 shows an example of phase counting mode 3 operation, and table 18.35 summarizes the TCNT up/down-count conditions.
Page 635: Figure 18.28 Example Of Phase Counting Mode 4 Operation
Table 18.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level High level Low level [Legend] : Rising edge : Falling edge • Phase counting mode 4 Figure 18.28 shows an example of phase counting mode 4 operation, and table 18.36 summarizes the TCNT up/down-count conditions.
Page 636: Table 18.36 Up/Down-Count Conditions In Phase Counting Mode 4
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level High level Low level [Legend] : Rising edge : Falling edge Phase Counting Mode Application Example: Figure 18.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed.
Page 637: Figure 18.29 Phase Counting Mode Application Example
Edge TCLKA detection TCLKB circuit Figure 18.29 Phase Counting Mode Application Example Section 18 Multi-Function Timer Pulse Unit (MTU) Channel 1 TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Rev.
Page 638: Reset-Synchronized Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter.
Page 639: Figure 18.30 Procedure For Selecting The Reset-Synchronized Pwm Mode
Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 18.30 shows an example of procedure for selecting the reset synchronized PWM mode. Reset-synchronized PWM mode Stop counting Select counter clock and counter clear source Brushless DC motor control setting Set TCNT Set TGR PWM cycle output enabling, PWM output level setting...
Page 640: Figure 18.31 Reset-Synchronized Pwm Mode Operation Example (When The Tocr's Olsn = 1 And Olsp = 1)
Section 18 Multi-Function Timer Pulse Unit (MTU) Reset-Synchronized PWM Mode Operation: Figure 18.31 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from H'0000.
Page 641: Complementary Pwm Mode
18.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period.
Page 642: Table 18.40 Register Settings For Complementary Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) Table 18.40 Register Settings for Complementary PWM Mode Channel Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1)
Page 643: Figure 18.32 Block Diagram Of Channels 3 And 4 In Complementary Pwm Mode
TGRC_3 TDDR TGRA_3 Comparator TCNT_3 TCNTS Comparator TGRD_3 TGRC_4 Figure 18.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode Section 18 Multi-Function Timer Pulse Unit (MTU) TCBR TCDR Match signal TCNT_4 Match signal TGRD_4 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by port E)
Page 644: Figure 18.33 Example Of Complementary Pwm Mode Setting Procedure
Section 18 Multi-Function Timer Pulse Unit (MTU) Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 18.33. Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting TCNT setting...
Page 645 Section 18 Multi-Function Timer Pulse Unit (MTU) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 18.34 illustrates counter operation in complementary PWM mode, and figure 18.35 shows an example of complementary PWM mode operation. Counter Operation: In complementary PWM mode, three counters−TCNT_3, TCNT_4, and TCNTS−perform up/down-count operations.
Page 646: Figure 18.34 Complementary Pwm Mode Counter Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) Counter value TGRA_3 TCDR TCNT_4 TCNTS TDDR H'0000 TCNT_3 TCNT_4 TCNTS Figure 18.34 Complementary PWM Mode Counter Operation Register Operation: In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 18.35 shows an example of complementary PWM mode operation.
Page 647: Figure 18.35 Example Of Complementary Pwm Mode Operation
with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters−TCNT_3, TCNT_4, and TCNTS−and two registers−compare register and temporary register−are compared, and PWM output controlled accordingly.
Page 648: Table 18.41 Registers And Counters Requiring Initialization
Section 18 Multi-Function Timer Pulse Unit (MTU) Initialization: In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td.
Page 649 Section 18 Multi-Function Timer Pulse Unit (MTU) Dead Time Setting: In complementary PWM mode, PWM pulses are output with a non- overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4.
Page 650: Figure 18.36 Example Of Pwm Cycle Updating
Section 18 Multi-Function Timer Pulse Unit (MTU) TGRC_3 Counter value update TGRA_3 Figure 18.36 Example of PWM Cycle Updating Register Data Updating: In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation.
Page 651: Figure 18.37 Example Of Data Update In Complementary Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) Figure 18.37 Example of Data Update in Complementary PWM Mode Rev. 4.00 Sep. 14, 2005 Page 601 of 982 REJ09B0023-0400...
Page 652: Figure 18.38 Example Of Initial Output In Complementary Pwm Mode (1)
Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR).
Page 653: Figure 18.39 Example Of Initial Output In Complementary Pwm Mode (2)
Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) Initial output Positive phase output Negative phase output Complementary PWM mode (TMDR setting) Figure 18.39 Example of Initial Output in Complementary PWM Mode (2) Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT_3, 4 value TDDR...
Page 654 Section 18 Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode PWM Output Generation Method: In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register.
Page 655: Figure 18.40 Example Of Complementary Pwm Mode Waveform Output (1)
Section 18 Multi-Function Timer Pulse Unit (MTU) T2 period T1 period T1 period TGR3A_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.40 Example of Complementary PWM Mode Waveform Output (1) Rev. 4.00 Sep. 14, 2005 Page 605 of 982 REJ09B0023-0400...
Page 656: Figure 18.41 Example Of Complementary Pwm Mode Waveform Output (2)
Section 18 Multi-Function Timer Pulse Unit (MTU) T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.41 Example of Complementary PWM Mode Waveform Output (2) Rev. 4.00 Sep. 14, 2005 Page 606 of 982 REJ09B0023-0400 T2 period T1 period...
Page 657: Figure 18.42 Example Of Complementary Pwm Mode Waveform Output (3)
Section 18 Multi-Function Timer Pulse Unit (MTU) T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.42 Example of Complementary PWM Mode Waveform Output (3) Rev. 4.00 Sep. 14, 2005 Page 607 of 982 REJ09B0023-0400...
Page 658: Figure 18.43 Example Of Complementary Pwm Mode 0% And 100% Waveform Output (1)
Section 18 Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode 0% and 100% Duty Output: In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 18.43 to 18.47 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state.
Page 659: Figure 18.44 Example Of Complementary Pwm Mode 0% And 100% Waveform Output (2)
T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Section 18 Multi-Function Timer Pulse Unit (MTU) T2 period T2 period...
Page 660: Figure 18.46 Example Of Complementary Pwm Mode 0% And 100% Waveform Output (4)
Section 18 Multi-Function Timer Pulse Unit (MTU) T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 18.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Rev.
Page 661: Figure 18.48 Example Of Toggle Output Waveform Synchronized With Pwm Output
Section 18 Multi-Function Timer Pulse Unit (MTU) Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 18.48.
Page 662: Figure 18.49 Counter Clearing Synchronized With Another Channel
Section 18 Multi-Function Timer Pulse Unit (MTU) Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel.
Page 663: Figure 18.50 Example Of Output Phase Switching By External Input (1)
Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 18.50 to 18.53 show examples of brushless DC motor drive waveforms created using TGCR.
Page 664: Figure 18.51 Example Of Output Phase Switching By External Input (2)
Section 18 Multi-Function Timer Pulse Unit (MTU) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BCD = 1, N = 1, P = 1, FB = 0, output active level = high Figure 18.51 Example of Output Phase Switching by External Input (2) TGCR UF bit...
Page 665: Figure 18.53 Example Of Output Phase Switching By Means Of Uf, Vf, Wf Bit Settings (2)
TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BCD = 1, N = 1, P = 1, FB = 1, output active level = high Figure 18.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3 compare-match or a compare-match on a channel other than channels 3 and 4.
Page 666: Interrupts
Section 18 Multi-Function Timer Pulse Unit (MTU) Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR;...
Page 667: Table 18.42 Mtu Interrupts
Table 18.42 MTU Interrupts Channel Name Interrupt Source TGI0A TGRA_0 input capture/compare match TGI0B TGRB_0 input capture/compare match TGI0C TGRC_0 input capture/compare match TGI0D TGRD_0 input capture/compare match TCI0V TCNT_0 overflow TGI1A TGRA_1 input capture/compare match TGI1B TGRB_1 input capture/compare match TCI1V TCNT_1 overflow TCI1U...
Page 668: Dma Activation
Section 18 Multi-Function Timer Pulse Unit (MTU) Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0.
Page 669: Operation Timing
18.6 Operation Timing 18.6.1 Input/Output Timing TCNT Count Timing: Figure 18.54 shows TCNT count timing in internal clock operation, and figure 18.55 shows TCNT count timing in external clock operation (normal mode), and figure 18.56 shows TCNT count timing in external clock operation (phase counting mode). Pφ...
Page 670: Figure 18.56 Count Timing In External Clock Operation (Phase Counting Mode)
Section 18 Multi-Function Timer Pulse Unit (MTU) Pφ External Falling edge clock TCNT input clock TCNT Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
Page 671: Figure 18.58 Output Compare Output Timing (Complementary Pwm Mode/Reset Synchronous Pwm Mode)
Pφ TCNT input clock TCNT Compare match signal TIOC pin Figure 18.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 18.59 shows input capture signal timing. Pφ Input capture input Input capture signal TCNT Figure 18.59 Input Capture Input Signal Timing Section 18 Multi-Function Timer Pulse Unit (MTU)
Page 672: Figure 18.60 Counter Clear Timing (Compare Match)
Section 18 Multi-Function Timer Pulse Unit (MTU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 18.60 shows the timing when counter clearing on compare match is specified, and figure 18.61 shows the timing when counter clearing on input capture is specified. Pφ...
Page 673: Figure 18.62 Buffer Operation Timing (Compare Match)
Buffer Operation Timing: Figures 18.62 and 18.63 show the timing in buffer operation. Pφ TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 18.62 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 18.63 Buffer Operation Timing (Input Capture) Section 18 Multi-Function Timer Pulse Unit (MTU) Rev.
Page 674: Interrupt Signal Timing
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 18.64 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. Pφ...
Page 675: Figure 18.66 Tciv Interrupt Setting Timing
TCFV Flag/TCFU Flag Setting Timing: Figure 18.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 18.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
Page 676: Figure 18.68 Timing For Status Flag Clearing By The Cpu
Section 18 Multi-Function Timer Pulse Unit (MTU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMA is activated, the flag is cleared automatically. Figure 18.68 shows the timing for status flag clearing by the CPU, and figure 18.69 shows the timing for status flag clearing by the DMA.
Page 677: Usage Notes
18.7 Usage Notes 18.7.1 Module Standby Mode Setting MTU operation can be disabled or enabled using the module standby register. 18.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection.
Page 678: Caution On Period Setting
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: Pφ...
Page 679: Conflict Between Tcnt Write And Increment Operations
18.7.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 18.72 shows the timing in this case. Pφ Address Write signal TCNT input clock...
Page 680: Conflict Between Tgr Write And Compare Match
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.6 Conflict between TGR Write and Compare Match When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is generated. Figure 18.73 shows the timing in this case.
Page 681: Figure 18.74 Conflict Between Buffer Register Write And Compare Match (Channel 0)
Pφ Address Write signal Compare match signal Compare match buffer signal Buffer register Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0) Pφ Address Write signal Compare match signal Compare match buffer signal Buffer register Figure 18.75 Conflict between Buffer Register Write and Compare Match Section 18 Multi-Function Timer Pulse Unit (MTU) TGR write cycle Buffer register...
Page 682: Conflict Between Tgr Read And Input Capture
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.8 Conflict between TGR Read and Input Capture If an input capture signal is generated in the T2 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 18.76 shows the timing in this case.
Page 683: Conflict Between Tgr Write And Input Capture
18.7.9 Conflict between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 18.77 shows the timing in this case. Pφ...
Page 684: 18.7.10 Conflict Between Buffer Register Write And Input Capture
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.10 Conflict between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 18.78 shows the timing in this case.
Page 685: Figure 18.79 Tcnt_2 Write And Overflow/Underflow Conflict With Cascade Connection
Pφ Address Write signal TCNT_2 TGR2A_2 to TGR2B_2 Ch2 compare- match signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare- match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection Section 18 Multi-Function Timer Pulse Unit (MTU) TCNT write cycle...
Page 686: 18.7.12 Counter Value During Complementary Pwm Mode Stop
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state.
Page 687: 18.7.14 Reset Sync Pwm Mode Buffer Operation And Compare Match Flag
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4, while the TCBR functions as the TCDR's buffer register. 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0.
Page 688: 18.7.15 Overflow Flags In Reset Sync Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting.
Page 689: 18.7.17 Conflict Between Tcnt Write And Overflow/Underflow
Pφ TCNT input clock TCNT Counter clear signal TCFV Figure 18.83 Conflict between Overflow and Counter Clearing 18.7.17 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Page 690: 18.7.18 Cautions On Transition From Normal Operation Or Pwm Mode 1 To
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset- synchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct.
Page 691: Mtu Output Pin Initialization
18.8 MTU Output Pin Initialization 18.8.1 Operating Modes The MTU has the following six operating modes. Waveform output is possible in all of these modes. • Normal mode (channels 0 to 4) • PWM mode 1 (channels 0 to 4) •...
Page 692: Operation In Case Of Re-Setting Due To Error During Operation, Etc
Section 18 Multi-Function Timer Pulse Unit (MTU) 18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level.
Page 693: Overview Of Initialization Procedures And Mode Transitions In Case Of Error During Operation, Etc
18.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.
Page 694: Figure 18.85 Error Occurrence In Normal Mode, Recovery In Normal Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 18.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. RESET TMDR TOER...
Page 695: Figure 18.86 Error Occurrence In Normal Mode, Recovery In Pwm Mode 1
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TOER...
Page 696: Figure 18.87 Error Occurrence In Normal Mode, Recovery In Pwm Mode 2
Section 18 Multi-Function Timer Pulse Unit (MTU) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 18.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
Page 697: Figure 18.88 Error Occurrence In Normal Mode, Recovery In Phase Counting Mode
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 18.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. RESET TMDR TOER...
Page 698: Figure 18.89 Error Occurrence In Normal Mode, Recovery In Complementary Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 699: Figure 18.90 Error Occurrence In Normal Mode, Recovery In Reset-Synchronous
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.90 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting. RESET TMDR TOER...
Page 700: Figure 18.91 Error Occurrence In Pwm Mode 1, Recovery In Normal Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 18.91 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
Page 701: Figure 18.92 Error Occurrence In Pwm Mode 1, Recovery In Pwm Mode 1
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.92 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TOER...
Page 702: Figure 18.93 Error Occurrence In Pwm Mode 1, Recovery In Pwm Mode 2
Section 18 Multi-Function Timer Pulse Unit (MTU) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.93 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
Page 703: Figure 18.94 Error Occurrence In Pwm Mode 1, Recovery In Phase Counting Mode
(10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 18.94 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. RESET TMDR TOER...
Page 704: Figure 18.95 Error Occurrence In Pwm Mode 1, Recovery In Complementary Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.95 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 705: Figure 18.96 Error Occurrence In Pwm Mode 1, Recovery In Reset-Synchronous
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.96 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting. RESET TMDR TOER...
Page 706: Figure 18.97 Error Occurrence In Pwm Mode 2, Recovery In Normal Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 18.97 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
Page 707: Figure 18.98 Error Occurrence In Pwm Mode 2, Recovery In Pwm Mode 1
(14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 18.98 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TIOR...
Page 708: Figure 18.99 Error Occurrence In Pwm Mode 2, Recovery In Pwm Mode 2
Section 18 Multi-Function Timer Pulse Unit (MTU) (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 18.99 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
Page 709: Figure 18.100 Error Occurrence In Pwm Mode 2, Recovery In Phase Counting Mode
(16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 18.100 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. RESET TMDR TIOR...
Page 710: Figure 18.101 Error Occurrence In Phase Counting Mode, Recovery In Normal Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 18.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 711: Figure 18.102 Error Occurrence In Phase Counting Mode, Recovery In Pwm Mode 1
(18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TIOR...
Page 712: Figure 18.103 Error Occurrence In Phase Counting Mode, Recovery In Pwm Mode 2
Section 18 Multi-Function Timer Pulse Unit (MTU) (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 18.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 713: Figure 18.104 Error Occurrence In Phase Counting Mode, Recovery In Phase Counting Mode
(20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 18.104 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. RESET TMDR TIOR...
Page 714: Figure 18.105 Error Occurrence In Complementary Pwm Mode, Recovery In
Section 18 Multi-Function Timer Pulse Unit (MTU) (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 18.105 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. RESET TOCR TMDR...
Page 715: Figure 18.106 Error Occurrence In Complementary Pwm Mode, Recovery In Pwm Mode 1
(22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.106 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. RESET TOCR TMDR...
Page 716: Figure 18.107 Error Occurrence In Complementary Pwm Mode, Recovery In Complementary Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.107 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
Page 717: Figure 18.108 Error Occurrence In Complementary Pwm Mode, Recovery In Complementary Pwm Mode
(24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.108 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
Page 718: Figure 18.109 Error Occurrence In Complementary Pwm Mode, Recovery In Reset-Synchronous Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.109 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode.
Page 719: Figure 18.110 Error Occurrence In Reset-Synchronous Pwm Mode, Recovery In
(26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 18.110 shows an explanatory diagram of the case where an error occurs in reset- synchronous PWM mode and operation is restarted in normal mode after re-setting. RESET TOCR TMDR...
Page 720: Figure 18.111 Error Occurrence In Reset-Synchronous Pwm Mode, Recovery In
Section 18 Multi-Function Timer Pulse Unit (MTU) (27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 18.111 shows an explanatory diagram of the case where an error occurs in reset- synchronous PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 721: Figure 18.112 Error Occurrence In Reset-Synchronous Pwm Mode, Recovery In Complementary Pwm Mode
(28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 18.112 shows an explanatory diagram of the case where an error occurs in reset- synchronous PWM mode and operation is restarted in complementary PWM mode after re-setting. RESET TOCR TMDR...
Page 722: Figure 18.113 Error Occurrence In Reset-Synchronous Pwm Mode, Recovery In Reset-Synchronous Pwm Mode
Section 18 Multi-Function Timer Pulse Unit (MTU) (29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 18.113 shows an explanatory diagram of the case where an error occurs in reset- synchronous PWM mode and operation is restarted in reset-synchronous PWM mode after re- setting.
Page 723: Port Output Enable (Poe)
18.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0 to POE3 pin input, depending on the output status of the high-current pins (TIOC3B/PTE[6], TIOC3D/PTE[4], TIOC4A/PTE[3], TIOC4B/PTE[2], TIOC4C/PTE[1], TIOC4D/PTE[0]).
Page 724: Figure 18.114 Poe Block Diagram
Section 18 Multi-Function Timer Pulse Unit (MTU) The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 18.114. TIOC3B Output level detection circuit TIOC3D TIOC4A Output level detection circuit TIOC4C TIOC4B Output level detection circuit TIOC4D Input level detection circuit...
Page 725: Pin Configuration
18.9.2 Pin Configuration Table 18.44 Pin Configuration Name Port output enable input pins Table 18.45 shows output-level comparisons with pin combinations. Table 18.45 Pin Combinations Pin Combination TIOC3B/PTE[6] and TIOC3D/PTE[4] Output All high-current pins are made high-impedance TIOC4A/PTE[3] and TIOC4C/PTE[1] Output All high-current pins are made high-impedance TIOC4B/PTE[2] and TIOC4D/PTE[0] Output All high-current pins are made high-impedance 18.9.3 Register Configuration...
Page 726 Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value POE3F POE2F POE1F POE0F Rev. 4.00 Sep. 14, 2005 Page 676 of 982 REJ09B0023-0400 Description R/(W)* POE3 Flag This flag indicates that a high impedance request has been input to the POE3 pin [Clear condition] •...
Page 727 Initial Bit Name value  11 to 9 All 0 POE3M1 POE3M0 POE2M1 POE2M0 Section 18 Multi-Function Timer Pulse Unit (MTU) Description Reserved These bits are always read as 0. The write value should always be 0. Port Interrupt Enable This bit enables/disables interrupt requests when any of the POE0F to POE3F bits of the ICSR1 are set to 1 0: Interrupt requests disabled...
Page 728 Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value POE1M1 POE1M0 POE0M1 POE0M0 Note: The write value should always be 0. Rev. 4.00 Sep. 14, 2005 Page 678 of 982 REJ09B0023-0400 Description POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses, and all are low...
Page 729 Output Level Control/Status Register (OCSR): OCSR is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. Initial Bit Name value...
Page 730 Section 18 Multi-Function Timer Pulse Unit (MTU) Initial Bit Name value  7 to 0 All 0 Note: * The write value should always be 0. Rev. 4.00 Sep. 14, 2005 Page 680 of 982 REJ09B0023-0400 Description Output Level Compare Enable This bit enables the start of output level comparisons.
Page 731: Operation
18.9.4 Operation Input Level Detection Operation: If the input conditions set by the ICSR1 occur on any of the POE0 to POE3 pins, all high-current pins become high-impedance state. However, only when the general input/output function or MTU function is selected, the large-current pin is in the high- impedance state.
Page 732: Figure 18.116 Low-Level Detection Operation
Section 18 Multi-Function Timer Pulse Unit (MTU) 2. Low-Level Detection Figure 18.116 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR1. If even one high level is detected during this interval, the low level is not accepted. Furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection.
Page 733 Section 18 Multi-Function Timer Pulse Unit (MTU) Release from High-Impedance State: High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High- current pins that have become high-impedance due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level compares, then clearing the bit 15 (OSF) flag.
Page 734 Section 18 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Sep. 14, 2005 Page 684 of 982 REJ09B0023-0400...
Page 735: Section 19 Serial Communication Interface With Fifo (Scif)
Section 19 Serial Communication Interface with FIFO 19.1 Overview This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication.
Page 736 Section 19 Serial Communication Interface with FIFO (SCIF) • Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. The direct memory access controller (DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receive- FIFO-data-full interrupt.
Page 737: Figure 19.1 Block Diagram Of Scif
SCFRDR SCFTDR (16 stage) (16 stage) SCRSR SCTSR Parity generation Parity check [Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register Figure 19.1 Block Diagram of SCIF Section 19 Serial Communication Interface with FIFO (SCIF) Module data bus SCBRRn...
Page 738: Pin Configuration
Section 19 Serial Communication Interface with FIFO (SCIF) 19.2 Pin Configuration The SCIF has the serial pins summarized in table 19.1. Table 19.1 SCIF Pins Channel Pin Name Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin Serial clock pin Receive data pin...
Page 739: Register Description
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3 Register Description The SCIF has the following registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. • Receive FIFO data register_0 (SCFRDR_0) • Transmit FIFO data register_0 (SCFTDR_0) •...
Page 740: Receive Shift Register (Scrsr)
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register.
Page 741: Transmit Fifo Data Register (Scftdr)
19.3.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR.
Page 742 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value Rev. 4.00 Sep. 14, 2005 Page 692 of 982 REJ09B0023-0400 Description Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Page 743 Initial Bit Name value STOP Section 19 Serial Communication Interface with FIFO (SCIF) Description Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking.
Page 744 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value  CKS1 CKS0 Rev. 4.00 Sep. 14, 2005 Page 694 of 982 REJ09B0023-0400 Description Reserved This bit is always read as 0. The write value should always be 0. Clock Select 1, 0 Select the internal clock source of the on-chip baud rate generator.
Page 745: Serial Control Register (Scscr)
19.3.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset. Initial Bit Name value...
Page 746 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value Rev. 4.00 Sep. 14, 2005 Page 696 of 982 REJ09B0023-0400 Description Receive Interrupt Enable Enables or disables the receive-data-full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when...
Page 747 Initial Bit Name value REIE Section 19 Serial Communication Interface with FIFO (SCIF) Description Receive Enable Enables or disables the SCIF serial receiver. 0: Receiver disabled* 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER).
Page 748 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value  CKE1 CKE0 Rev. 4.00 Sep. 14, 2005 Page 698 of 982 REJ09B0023-0400 Description Reserved This bit is always read as 0. The write value should always be 0. Clock Enable 1, 0 Select the SCIF clock source and enable or disable clock output from the SCK pin.
Page 749: Serial Status Register (Scfsr)
19.3.7 Serial Status Register (SCFSR) The serial status register (SCFSR) is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR data, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR).
Page 750 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value Rev. 4.00 Sep. 14, 2005 Page 700 of 982 REJ09B0023-0400 Description R/(W)* Receive Error Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. * 0: Receiving is in progress or has ended normally [Clearing conditions] •...
Page 751 Initial Bit Name value TEND Section 19 Serial Communication Interface with FIFO (SCIF) Description R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition] •...
Page 752 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value TDFE Rev. 4.00 Sep. 14, 2005 Page 702 of 982 REJ09B0023-0400 Description R/(W)* Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0...
Page 753 Initial Bit Name value Section 19 Serial Communication Interface with FIFO (SCIF) Description R/(W)* Break Detection Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions] • BRK is cleared to 0 when the chip is a power-on reset •...
Page 754 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value Rev. 4.00 Sep. 14, 2005 Page 704 of 982 REJ09B0023-0400 Description Parity Error Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode.
Page 755 Initial Bit Name value Section 19 Serial Communication Interface with FIFO (SCIF) Description R/(W)* Receive FIFO Data Full Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR).
Page 756 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value Note: The only value that can be written is 0 to clear the flag. Rev. 4.00 Sep. 14, 2005 Page 706 of 982 REJ09B0023-0400 Description R/(W)* Receive Data Ready Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not...
Page 757: Bit Rate Register (Scbrr)
19.3.8 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR.
Page 758: Table 19.3 Bit Rates And Scbrr Settings In Asynchronous Mode
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.3 lists examples of SCBRR settings in asynchronous mode, and table 19.4 lists examples of SCBRR settings in synchronous mode. Table 19.3 Bit Rates and SCBRR Settings in Asynchronous Mode Bit Rate (bits/s) n 1200 2400 4800...
Page 759 Bit Rate Error (bits/s) –0.25 2 0.16 0.16 0.16 1200 0.16 2400 0.16 4800 0.16 9600 –1.36 0 19200 1.73 31250 0.00 38400 1.73 Bit Rate Error (bits/s) 0.03 0.16 0.16 0.16 1200 0.16 2400 0.16 4800 0.16 9600 0.16 19200 0.16 31250...
Page 760 Section 19 Serial Communication Interface with FIFO (SCIF) 24.576 Bit Rate Error (bits/s) 0.08 0.00 0.00 0.00 1200 0.00 2400 0.00 4800 0.00 9600 0.00 19200 0.00 31250 –1.70 0 38400 0.00 Note: Settings with an error of 1% or less are recommended. Rev.
Page 761: Table 19.4 Bit Rates And Scbrr Settings In Synchronous Mode
Table 19.4 Bit Rates and SCBRR Settings in Synchronous Mode Bit Rate (bits/s) — — — 2.5k 100k — — 250k 500k — — — — — — [Legend] Blank: No setting possible —: Setting possible, but error occurs Note: Set the BRR value that satisfies the external specifications.
Page 762: Table 19.5 Maximum Bit Rates For Various Frequencies With Baud Rate Generator (Asynchronous Mode)
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 19.6 and 19.7 list the maximum rates for external clock input. Table 19.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Pφ...
Page 763: Table 19.6 Maximum Bit Rates With External Clock Input (Asynchronous Mode)
Table 19.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) 4.9152 9.8304 14.7456 19.6608 24.576 28.7 Table 19.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) Pφ (MHz) 28.7 Section 19 Serial Communication Interface with FIFO (SCIF) External Input Clock (MHz) 1.2500 1.2288...
Page 764: Fifo Control Register (Scfcr)
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.9 FIFO Control Register (SCFCR) The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU.
Page 765 Initial Bit Name value RTRG1 RTRG0 TTRG1 TTRG0 Section 19 Serial Communication Interface with FIFO (SCIF) Description Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR).
Page 766 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value TFRST RFRST LOOP Rev. 4.00 Sep. 14, 2005 Page 716 of 982 REJ09B0023-0400 Description Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state.
Page 767: Fifo Data Count Register (Scfdr)
19.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits.
Page 768 Section 19 Serial Communication Interface with FIFO (SCIF) Initial Bit Name value 15 to 8 — All 0 RTSIO RTSDT CTSIO CTSDT Rev. 4.00 Sep. 14, 2005 Page 718 of 982 REJ09B0023-0400 Description Reserved These bits are always read as 0. The write value should always be 0.
Page 769 Initial Bit Name value SCKIO SCKDT SPB2IO SPB2DT Section 19 Serial Communication Interface with FIFO (SCIF) Description SCK Port Input/Output Indicates the input or output of SCK pin. When SCK pin is used as port outputting the SCKDT bit, the CKE1, CKE0 bit of serial control register (SCSCR) should be set to 0.
Page 770: Line Status Register (Sclsr)
Section 19 Serial Communication Interface with FIFO (SCIF) 19.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset.
Page 771: Operation
19.4 Operation 19.4.1 Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication.
Page 772: Table 19.8 Scsmr Settings And Scif Communication Formats
Section 19 Serial Communication Interface with FIFO (SCIF) Table 19.8 SCSMR Settings and SCIF Communication Formats SCSMR Settings Bit 7 Bit 6 Bit 5 Bit 3 STOP Mode Asynchronous Synchronous Note: *: Don't care Table 19.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR SCSCR Settings...
Page 773: Operation In Asynchronous Mode
19.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible.
Page 774: Table 19.10 Serial Communication Formats (Asynchronous Mode)
Section 19 Serial Communication Interface with FIFO (SCIF) Transmit/Receive Formats: Table 19.10 lists the 8 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 19.10 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR PE STOP START...
Page 775 Section 19 Serial Communication Interface with FIFO (SCIF) Transmitting and Receiving Data: • SCIF Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 776: Figure 19.3 Sample Flowchart For Scif Initialization
Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.3 shows a sample flowchart for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 After reading BRK, DR, and ER flags in SCFSR, and each flag in SCLSR, write 0 to clear them Set CKE1 and CKE0 bits...
Page 777: Figure 19.4 Sample Flowchart For Transmitting Serial Data
• Transmitting Serial Data (Asynchronous Mode) Figure 19.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission Read TDFE flag in SCFSR TDFE = 1? Write transmit data in SCFTDR, and read 1 from TDFE flag and TEND flag in SCFSR,...
Page 778 Section 19 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR.
Page 779: Figure 19.5 Example Of Transmit Operation (8-Bit Data, Parity, One Stop Bit)
Figure 19.5 shows an example of the operation for transmission. Start Serial data TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 19.5 Example of Transmit Operation 4.
Page 780: Figure 19.7 Sample Flowchart For Receiving Serial Data
Section 19 Serial Communication Interface with FIFO (SCIF) • Receiving Serial Data (Asynchronous Mode) Figures 19.7 and 19.8 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR...
Page 781: Figure 19.8 Sample Flowchart For Receiving Serial Data (Cont)
Section 19 Serial Communication Interface with FIFO (SCIF) Error handling ORER = 1? Overrun error handling ER = 1? Receive error handling BRK = 1? Break handling DR = 1? Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0 Figure 19.8 Sample Flowchart for Receiving Serial Data (cont)
Page 782 Section 19 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3.
Page 783: Synchronous Operation
Start Serial data One frame Figure 19.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS signal is output depending on the empty status of SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR exceeds the number set for the RTS output active trigger.
Page 784: Figure 19.11 Data Format In Synchronous Communication
Section 19 Serial Communication Interface with FIFO (SCIF) Figure 19.11 shows the general format in synchronous serial communication. Synchronization clock Serial data Don’t care Note: * High except in continuous transfer Figure 19.11 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next.
Page 785: Figure 19.12 Sample Flowchart For Scif Initialization
Figure 19.12 shows a sample flowchart for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR, write 0 to clear them Set data transfer format...
Page 786: Figure 19.13 Sample Flowchart For Transmitting Serial Data
Section 19 Serial Communication Interface with FIFO (SCIF) • Transmitting Serial Data (Synchronous Mode) Figure 19.13 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission Read TDFE flag in SCFSR TDFE = 1? Write transmit data to SCFTDR...
Page 787: Figure 19.14 Example Of Scif Transmit Operation
In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR.
Page 788: Figure 19.15 Sample Flowchart For Receiving Serial Data (1)
Section 19 Serial Communication Interface with FIFO (SCIF) • Receiving Serial Data (Synchronous Mode) Figure 19.15 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0.
Page 789: Figure 19.16 Sample Flowchart For Receiving Serial Data (2)
Section 19 Serial Communication Interface with FIFO (SCIF) Error handling ORER = 1? Overrun error handling Clear ORER flag in SCLSR to 0 Figure 19.16 Sample Flowchart for Receiving Serial Data (2) Rev. 4.00 Sep. 14, 2005 Page 739 of 982 REJ09B0023-0400...
Page 790: Figure 19.17 Example Of Scif Receive Operation
Section 19 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts the reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not.
Page 791: Figure 19.18 Sample Flowchart For Transmitting/Receiving Serial Data
• Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode) Figure 19.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling the SCIF for transmission/reception. Initialization Start of transmission and reception Read TDFE flag in SCFSR TDFE = 1?
Page 792: Scif Interrupts And Dmac
Section 19 Serial Communication Interface with FIFO (SCIF) 19.5 SCIF Interrupts and DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 19.11 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR.
Page 793: Usage Notes
Table 19.11 SCIF Interrupt Sources Interrupt Source Description Interrupt initiated by receive error (ER) Interrupt initiated by receive data FIFO full (RDF) or data ready (DR)* Interrupt initiated by break (BRK) or overrun error (ORER) Interrupt initiated by transmit FIFO data empty (TDFE) Note: RXI interrupt by DR is only possible in the asynchronous mode.
Page 794 Section 19 Serial Communication Interface with FIFO (SCIF) The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). 3. Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected.
Page 795: Figure 19.19 Receive Data Sampling Timing In Asynchronous Mode
16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 Base clock Receive data Start bit (RxD)
Page 796: Figure 19.20 Dma Transfer Example In The Synchronization Clock
Section 19 Serial Communication Interface with FIFO (SCIF) 6. When Using the DMAC  Using an External Clock in Chock Synchronous Mode: When using an external clock as the synchronization clock, after SCFTDR is updated by the DMAC, an external clock should be input after at least five peripheral clock cycles. A malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR (figure 19.20).
Page 797: Section 20 Usb Function Module
Section 20 USB Function Module 20.1 Features • Incorporates UDC (USB device controller) conforming to the USB standard Automatic processing of USB protocol Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) •...
Page 798: Block Diagram
Section 20 USB Function Module • Power mode: Self-powered, bus-powered 20.1.1 Block Diagram Internal peripheral bus Interrupt requests DMA transfer requests Clock (48 MHz) UDC: USB device controller 20.2 Pin Configuration Table 20.1 Pin Configuration and Functions Pin Name Function XVDATA Input Input pin for receive data from differential receiver...
Page 799: Register Descriptions
Section 20 USB Function Module In on-chip transceiver bypass mode (the XVEROFF bit of the USBXVERCR register is 1), a Philips PDIUSBP11 Series transceiver or compatible product can be connected (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand).
Page 800: Usb Interrupt Flag Register 0 (Usbifr0)
Section 20 USB Function Module 20.3.1 USB Interrupt Flag Register 0 (USBIFR0) Together with USB interrupt flag registers 1 (USBIFR1) and 2 (USBIFR2), USBIFR0 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 0 (USBIER0).
Page 801: Usb Interrupt Flag Register 1 (Usbifr1)
Initial Bit Name Value EP0oTS EP0iTR EP0iTS 20.3.2 USB Interrupt Flag Register 1 (USBIFR1) Together with USB interrupt flag registers 0 (USBIFR0) and 2 (USBIFR2), USBIFR1 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 1 (USBIER1).
Page 802: Usb Interrupt Flag Register 2 (Usbifr2)
Section 20 USB Function Module Initial Bit Name Value EP3TR EP3TS VBUS 20.3.3 USB Interrupt Flag Register 2 (USBIFR2) Together with USB interrupt flag registers 0 (USBIFR0) and 1 (USBIFR1), USBIFR2 indicates interrupt status information required by the application. When an interrupt occurs, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with USB interrupt enable register 2 (USBIER2).
Page 803: Usb Interrupt Select Register 0 (Usbisr0)
Initial Bit Name Value CFGV SETC 20.3.4 USB Interrupt Select Register 0 (USBISR0) USBISR0 selects the vector numbers of the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR0 is cleared to 0, the interrupt will be USI0 (USB interrupt 0).
Page 804: Usb Interrupt Select Register 1 (Usbisr1)
Section 20 USB Function Module 20.3.5 USB Interrupt Select Register 1 (USBISR1) USBISR1 selects the vector numbers of the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). If the USB issues an interrupt request to the INTC when the corresponding bit in USBISR1 is cleared to 0, the interrupt will be USI0 (USB interrupt 0).
Page 805: Usb Interrupt Enable Register 1 (Usbier1)
20.3.7 USB Interrupt Enable Register 1 (USBIER1) USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1). When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is decided by the contents of USB interrupt select register 1 (USBISR1).
Page 806: Usbep0I Data Register (Usbepdr0I)
Section 20 USB Function Module 20.3.9 USBEP0i Data Register (USBEPDR0i) USBEPDR0i is an 8-byte transmit FIFO buffer for endpoint 0, holding one packet of transmit data for control IN. Transmit data is fixed by writing one packet of data and setting the EP0iPKTE bit in the trigger register.
Page 807: Usbep0S Data Register (Usbepdr0S)
20.3.11 USBEP0s Data Register (USBEPDR0s) USBEPDR0s is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception and stores an 8-byte command data that is sent in the setup stage. USBEPDR0s receives only commands requiring processing on the microcomputer (firmware) side. Commands that this module automatically processes are not stored.
Page 808: Usbep2 Data Register (Usbepdr2)
Section 20 USB Function Module 20.3.13 USBEP2 Data Register (USBEPDR2) USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and the EP2PKTE bit in the USB trigger register is set, one packet of transmit data is fixed, and the dual buffer is switched over.
Page 809: Usbep1 Receive Data Size Register (Usbepsz1)
20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1) USBEPSZ1 indicates, in bytes, the amount of data received from the host by endpoint 1. The endpoint 1 FIFO buffer has a dual-FIFO configuration. The receive data size indicated by this register refers to the currently selected FIFO (that can be read by CPU). USBEPSZ1 can be initialized to H'00 by a power-on reset.
Page 810: Usb Data Status Register (Usbdasts)
Section 20 USB Function Module Initial Bit Name Value EP0sRDFN EP0oRDFN EP0iPKTE 20.3.18 USB Data Status Register (USBDASTS) USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set to 1 when data is written to the corresponding FIFO buffer and the packet enable state is set. This bit is cleared when all data has been transmitted to the host.
Page 811: Usbfifo Clear Register (Usbfclr)
Initial Bit Name Value EP2DE  3 to 1 All 0 EP0iDE 20.3.19 USBFIFO Clear Register (USBFCLR) USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transmission/reception.
Page 812: Usbdma Transfer Setting Register (Usbdmar)
Section 20 USB Function Module Initial Bit Name Value EP0iCLR 20.3.20 USBDMA Transfer Setting Register (USBDMAR) USBDMAR enables DMA transfer between the endpoint 1 and endpoint 2 data registers and memory by means of the on-chip DMA controller (DMAC). Dual address transfer is performed with the transfer size of only on a per-byte basis.
Page 813: Usb Endpoint Stall Register (Usbepstl)
Initial Bit Name Value EP1DMAE 20.3.21 USB Endpoint Stall Register (USBEPSTL) The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data for which decoding is performed in this function module.
Page 814: Usb Transceiver Control Register (Usbxvercr)
Section 20 USB Function Module Initial Bit Name Value EP2STL EP1STL EP0STL 20.3.22 USB Transceiver Control Register (USBXVERCR) The USB transceiver control register (USBXVERCR) selects the on-chip transceiver or the external transceiver. Make sure to check if USBIFR1/VBUSMN=0 (VBUS pin disconnection) to overwrite this register.
Page 815: Usb Bus Power Control Register (Usbctrl)
20.3.23 USB Bus Power Control Register (USBCTRL) This LSI can operate using a bus power control method. For details of the bus power control method, see section 20.9, USB Bus Power Control Method. USBCTRL can be initialized to H'00 by a power-on reset. Initial Bit Name Value...
Page 816: Operation
Section 20 USB Function Module 20.4 Operation 20.4.1 Cable Connection USB function Cable disconnected VBUS pin = 0 V UDC core reset USB cable connection General output port D+ pull-up enabled? USBIFR1/VBUS = 1 USB bus connection interrupt UDC core reset release Bus reset reception USBIFR0/BRST = 1 Bus reset interrupt...
Page 817: Cable Disconnection
Also, in applications that require connection detection regardless of D+ pull-up control, detection should be carried out using IRQx or a general input port. For details, see section 20.8, Example of USB External Circuitry. 20.4.2 Cable Disconnection USB function Cable connected VBUS pin = 1 USB cable disconnection VBUS pin = 0...
Page 818: Control Transfer
Section 20 USB Function Module 20.4.3 Control Transfer Control transfer consists of three stages: setup, data (not always included), and status (figure 20.4). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below. Setup stage Control IN SETUP(0)
Page 819: Figure 20.5 Setup Stage Operation
Setup Stage: USB function SETUP token reception Receive 8-byte command data in EP0s Command to be processed by application? Set setup command reception complete flag (USBIFR0/SETUP TS = 1) To data stage Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.).
Page 820: Figure 20.6 Data Stage (Control-In) Operation
Section 20 USB Function Module Data Stage (Control-IN): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (USBIFR0/EP0iTS = 1).
Page 821: Figure 20.7 Data Stage (Control-Out) Operation
Data Stage (Control-OUT): The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is OUT-transfer, the application waits for data from the host, and after data is received (USBIFR0/EP0oTS = 1), reads data from the FIFO.
Page 822: Figure 20.8 Status Stage (Control-In) Operation
Section 20 USB Function Module Status Stage (Control-IN): The control-IN status stage starts with an OUT token from the host. The application receives 0-byte data from the host, and ends control transfer. USB function Application OUT token reception 0-byte reception from host Set EP0o reception Clear EP0o reception Interrupt request...
Page 823: Figure 20.9 Status Stage (Control-Out) Operation
Status Stage (Control-OUT): The control-OUT status stage starts with an IN token from the host. When an IN token is received at the start of the status stage, there is not yet any data in the EP0iFIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started.
Page 824: Ep1 Bulk-Out Transfer (Dual Fifos)
Section 20 USB Function Module 20.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs) EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately.
Page 825: Figure 20.10 Ep1 Bulk-Out Transfer Operation
USB function OUT token reception Space in EP1 FIFO? NACK Data reception from host Interrupt request Set EP1 FIFO full status (USBIFR0/EP1 FULL = 1) Both Interrupt request EP1 FIFOs empty? Clear EP1 FIFO full status (USBIFR0/EP1 FULL = 0) Figure 20.10 EP1 Bulk-OUT Transfer Operation Section 20 USB Function Module Application...
Page 826: Ep2 Bulk-In Transfer (Dual Fifos)
Section 20 USB Function Module 20.4.5 EP2 Bulk-IN Transfer (Dual FIFOs) EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO.
Page 827: Figure 20.11 Ep2 Bulk-In Transfer Operation
USB function IN token reception Valid data in EP2 FIFO? NACK Data transmission to host Space in EP2 FIFO? Clear EP2 empty status (USBIFR0/EP2 EMPTY = 0) Figure 20.11 EP2 Bulk-IN Transfer Operation Section 20 USB Function Module Application Clear EP2 transfer Interrupt request (USBIFR0/EP2 TR = 0) Enable EP2 FIFO...
Page 828: Ep3 Interrupt-In Transfer
Section 20 USB Function Module 20.4.6 EP3 Interrupt-IN Transfer USB function IN token reception Valid data in EP3 FIFO? Data transmission to host Set EP3 transmission complete flag (USBIFR1/EP3 TS = 1) Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Page 829: Processing Of Usb Standard Commands And Class/Vendor Commands
20.5 Processing of USB Standard Commands and Class/Vendor Commands 20.5.1 Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 20.2 below.
Page 830: Stall Operations
Section 20 USB Function Module 20.6 Stall Operations This section describes stall operations in the USB function module. There are two cases in which the USB function module stall function is used: • When the application forcibly stalls an endpoint for some reason •...
Page 831: Figure 20.13 Forcible Stall By Application
(1) Transition from normal operation to stall (1-1) Internal status bit (1-2) Transaction request Internal status bit (1-3) STALL handshake Internal status bit (2) When Clear Feature is sent after USBEPSTL is cleared (2-1) Transaction request Internal status bit (2-2) STALL handshake Internal status bit (2-3)
Page 832: Automatic Stall By Usb Function Module
Section 20 USB Function Module 20.6.2 Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to USBEPSTL register, and returns a stall handshake (1-1 in figure 20.14).
Page 833: Figure 20.14 Automatic Stall By Usb Function Module
(1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit (2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit (2-2) STALL handshake Internal status bit (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command...
Page 834: Dma Transfer
Section 20 USB Function Module 20.7 DMA Transfer This module allows DMAC transfer for endpoints 1 and 2, excluding transfer of word and longword. If endpoint 1 contains at least one byte of valid receive data, a DMA transfer request is issued to endpoint 1.
Page 835: Dma Transfer For Endpoint 2
20.7.2 DMA Transfer for Endpoint 2 When the transmitted data for EP2 is transferred by DMA when the data on one side of FIFO (64 bytes) becomes full an equivalent processing of writing 1 to the USBTRG/PKTE bit is automatically performed in the module. Therefore, when data to be transferred is a multiple of 64 bytes, writing 1 to the USBTRG/PKTE bit is not necessary.
Page 836: Example Of Usb External Circuitry
Section 20 USB Function Module 20.8 Example of USB External Circuitry USB Transceiver: When an on-chip transceiver is not used, a USB transceiver IC (such as a PDIUSBP11) must be connected externally. The USB transceiver manufacturer should be consulted concerning the recommended circuit from the USB transceiver to the USB connector, etc.
Page 837: Figure 20.17 Example Of Usb Function Module External Circuitry (For On-Chip Transceiver)
This LSI General output port, etc. USB module 3.3 V VBUS IC that allows voltage application when the system (LSI) power is off. Note: Operation cannot be guaranteed by this example. When the system requires countermeasures against external surge or ESD noise, use the protection diode or noise canceller. Figure 20.17 Example of USB Function Module External Circuitry (For On-Chip Transceiver) Section 20 USB Function Module...
Page 838: Figure 20.18 Example Of Usb Function Module External Circuitry (For External Transceiver)
Section 20 USB Function Module This LSI General output port, etc. USB module VBUS TXENL TXDMNS TXDPLS XVDATA DPLS DMNS SUSPND Note: Operation cannot be guaranteed by this example. When the system requires countermeasures against external surge or ESD noise, use the protection diode or noise canceller. Figure 20.18 Example of USB Function Module External Circuitry Rev.
Page 839: Usb Bus Power Control Method
20.9 USB Bus Power Control Method 20.9.1 USB Bus Power Control Operation This LSI can operate using a USB bus power control method. The following describes notes on the LSI using the USB bus power control method. Changing to High-Power Function: According to the USB standard, the startup operation (from connecting cables to completing enumeration) is handled as a low-power function.
Page 840: Usage Example Of Usb Bus Power Control Method
Section 20 USB Function Module This LSI IRQ1 USB suspend signal (internal signal) USBIFR2/ IRQ0 AWAKE signal (internal signal) USBIFR2/ Figure 20.19 IRQ0 and IRQ1 Interrupt Circuitry Normal IRQ1 interrupt operation routine Peripheral clock IRQ1_USB SUSPEND IRQ1 interrupt detected IRQ0_ AWAKE instruction issued Figure 20.20 USB Standby Operation Timing...
Page 841: Figure 20.21 Sample Flowchart For Initialization Of The Usb Bus Power Control Method
Normal routine Power On Reset Set STBCR4/MSTP46 to 1 (exit USB module stop mode) Set USBCTRL/PWMD to 1 (set to bus power control method) Set IPRC/IRQ0 of INTC to 15 (set the priority of IRQ0 to 15) Set IPRC/IRQ1 of INTC to 14 (set the priority of IRQ1 to 14) Clear ICR1/IRQ00S and IRQ01S of INTC to 0...
Page 842: Figure 20.22 Sample Flowchart For Changing The State From Usb Suspend To Standby
Section 20 USB Function Module Normal routine Normal state IRQ1 interrupt? Normal operation Figure 20.22 Sample Flowchart for Changing the State from USB Suspend to Standby Rev. 4.00 Sep. 14, 2005 Page 792 of 982 REJ09B0023-0400 IRQ1 interrupt routine Clear IRR0/IRQ1R of INTC Save SSR and SPC to memory Set SR/I[3:0] to the IRQ1...
Page 843: Figure 20.23 Sample Flowchart For Awake
Section 20 USB Function Module Normal routine IRQ1interrupt routine IRQ0 interrupt routine Normal state or standby mode IRQ0 interrupt? Clear IRR0/IRQ0R of INTC Set SR/I[3:0] to the IRQ0 priority IRR0/IRQ1R of INTC? Clear USBIFR2/SUSPS Clear IRR0/IRQ1R of INTC and AWAKE Clear USBIFR2/SUSPS RTE instruction and AWAKE...
Page 844: Notes On Usage
Section 20 USB Function Module 20.10 Notes on Usage 20.10.1 Receiving Setup Data Note that the following when 8-byte setup data is received by USBEPDR0s. 1. The USB must always receive the setup command. Therefore, writing from the USB bus has priority over reading from the CPU.
Page 845: 20.10.4 Assigning Interrupt Source For Ep0
20.10.4 Assigning Interrupt Source for EP0 Interrupt sources (bits 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be assigned to the same interrupt pin using USBISR0. 20.10.5 Clearing FIFO when Setting DMA Transfer Clearing the endpoint 1 data register (USBEPDR1) is impossible when DMA transfer is enabled (USBDMAR/EP1DMAE = 1) for endpoint 1.
Page 846: Figure 20.24 Timing For Setting The Tr Interrupt Flag
Section 20 USB Function Module IN token Host Check NAK Set TR flag Figure 20.24 Timing for Setting the TR Interrupt Flag Rev. 4.00 Sep. 14, 2005 Page 796 of 982 REJ09B0023-0400 TR interrupt routine TR interrupt routine Clear TR flag, Write transmit data, and TRG/PKTE IN token Check NAK...
Page 847: Section 21 A/D Converter
Section 21 A/D Converter This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. The A/D converter is composed of two independent modules, A/D0 and A/D1. 21.1 Features A/D converter features are listed below. •...
Page 848: Block Diagram
Section 21 A/D Converter 21.1.1 Block Diagram Figure 21.1 shows a block diagram of the A/D converter. AVcc and AVss for both A/D modules are common pins in the chip. A/D converter 0 10 bit Analog multi plecer Sample and- hold circuit A/D converter 1 10 bit...
Page 849: Input Pins
21.1.2 Input Pins Table 21.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: A/D0 (AN0 to AN3), and A/D1 (AN4 to AN7). AV inputs for the analog circuits in the A/D converter. AV reference voltage pin.
Page 850: Register Configuration
Section 21 A/D Converter 21.1.3 Register Configuration The A/D converter's registers are summarized below. • A/D0 data register A (ADDRA0) • A/D0 data register B (ADDRB0) • A/D0 data register C (ADDRC0) • A/D0 data register D (ADDRD0) • A/D0 control/status register (ADCSR0) •...
Page 851: A/D Control/Status Registers (Adcsr0, Adcsr1)
Table 21.2 Analog Input Channels and A/D Data Registers Analog Input Channel 21.2.2 A/D Control/Status Registers (ADCSR0, ADCSR1) ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter, and enable or disable starting of A/D conversion by external trigger input. ADCSR is initialized to H'0040 by a power-on reset and in standby mode.
Page 852 Section 21 A/D Converter Initial Bit Name Value ADIE ADST DMASL TRGE Rev. 4.00 Sep. 14, 2005 Page 802 of 982 REJ09B0023-0400 Description A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made.
Page 853 Initial Bit Name Value  10 to 8 All 0 CKS1 CKS0 MULTI1 MULTI0  3, 2 All 0 Description Reserved These bits are always read as 0. The write value should always be 0. Clock Select Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversion time.
Page 854: A/D0, A/D1 Control Register (Adcr)
Section 21 A/D Converter Initial Bit Name Value Note: Clear this bit by writing 0. 21.2.3 A/D0, A/D1 Control Register (ADCR) ADCR is a 16-bit readable/writable register that selects the simultaneous sampling of two channels. See section 21.3.4 Simultaneous Sampling Operation, for details on simultaneous sampling.
Page 855: Operation
21.3 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 21.3.1 Single Mode Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software.
Page 856: Multi Mode
Section 21 A/D Converter ADIE A/D conversion starts ADST Channel 0 (AN0) Waiting operating Channel 1 (AN1) Waiting operating A/D conversion 1 Channel 2 (AN2) Waiting operating Channel 3 (AN3) Waiting operating ADDRA ADDRB ADDRC ADDRD Note: * Vertical arrows ( ) indicate instruction execution by software. Figure 21.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 21.3.2 Multi Mode...
Page 857: Figure 21.3 Example Of A/D Converter Operation (Multi Mode, Channels An0 To An2 Selected)
Typical operations when three channels in A/D0 (AN0 to AN2) are selected in multi mode are described next. Figure 21.3 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1), channel group A/D0 is selected, analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
Page 858: Scan Mode
Section 21 A/D Converter 21.3.3 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR0 or ADCSR1) is set to 1 by software, A/D conversion starts on the first channel in the group (A/D0 when AN0, A/D1 when AN4).
Page 859: Simultaneous Sampling Operation
ADST Channel 0 (AN0) Waiting operating A/D conversion 1 Channel 1 (AN1) Waiting operating Channel 2 (AN2) Waiting operating Channel 3 (AN3) Waiting operating ADDRA0 ADDRB0 ADDRC0 ADDRD0 Notes: 1. Vertical arrows ( ) indicate instruction execution by software. 2. A/D conversion data is invalid/ Figure 21.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 21.3.4...
Page 860: A/D Converter Activation By Mtu
Section 21 A/D Converter 21.3.5 A/D Converter Activation by MTU The A/D converter can be independently activated by an A/D conversion request from the MTU or CSL. To activate the A/D converter by the MTU, set the A/D trigger enable bit (TRGE). After this bit setting has been made, the ADST bit in ADCSR is automatically set to 1 and A/D conversion is started when an A/D conversion request from the MTU occurs.
Page 861: Figure 21.5 A/D Conversion Timing
write cycle Pφ Address Write signal Input sampling timing [Legend] A/D conversion start delay Input sampling time : A/D conversion time CONV Table 21.3 A/D Conversion Time (Single Mode) Symbol A/D conversion start delay Input sampling time A/D conversion CONV time Note: Values in the table are numbers of states (t Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
Page 862: Interrupt And Dmac Transfer Request
Section 21 A/D Converter 21.4 Interrupt and DMAC Transfer Request The A/D converter generates an interrupt (ADI0 and ADI1) or DMAC activation signal at the end of A/D conversion. These requests are enabled or disabled by the ADIE bit or the DMASL bit in ADCSR.
Page 863: Definitions Of A/D Conversion Accuracy
Section 21 A/D Converter 21.5 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value.
Page 864: Figure 21.6 Definitions Of A/D Conversion Accuracy
Section 21 A/D Converter Digital output Ideal A/D conversion characteristic (3) Quantization error 1024 1024 FS: Full-scale voltage Figure 21.6 Definitions of A/D Conversion Accuracy Rev. 4.00 Sep. 14, 2005 Page 814 of 982 REJ09B0023-0400 Digital output 1022 1023 Analog input 1024 1024 voltage...
Page 865: Usage Notes
21.6 Usage Notes When using the A/D converter, note the following points. 21.6.1 Setting Analog Input Voltage Permanent damage to the LSI may result if the following voltage ranges are exceeded. 1. Analog input range: During A/D conversion, voltages on the analog input pins ANn should not go beyond the following range: AVss ≤...
Page 866: Influences On Absolute Precision
Section 21 A/D Converter 21.6.4 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas).
Page 867: Figure 21.7 Example Of Analog Input Protection Circuit
100 Ω 0.1 µF Note: Value are referene value. 10 µF 2. R : input impedance Figure 21.7 Example of Analog Input Protection Circuit AN0 to AN7 Note: Value are referene value. Figure 21.8 Analog Input Pin Equivalent Circuit Sensor output impeddance Up to 3 kΩ...
Page 868 Section 21 A/D Converter Rev. 4.00 Sep. 14, 2005 Page 818 of 982 REJ09B0023-0400...
Page 869: Section 22 Pin Function Controller (Pfc)
Section 22 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 22.1 lists the multiplexed pins.
Page 870 Section 22 Pin Function Controller (PFC) Port Port Function (Related Module) PTC15 input/output (port) PTC14 input/output (port) PTC13 input/output (port) PTC12 input/output (port) PTC11 input/output (port) PTC10 input/output (port) PTC9 input/output (port) PTC8 input/output (port) PTC7 input/output (port) PTC6 input/output (port) PTC5 input/output (port) PTC4 input/output (port) PTC3 input/output (port)
Page 871 Port Port Function (Related Module) PTE15 input/output (port) PTE14 input/output (port) PTE13 input/output (port) PTE12 input/output (port) PTE11 input/output (port) PTE10 input/output (port) PTE9 input/output (port) PTE8 input/output (port) PTE7 input/output (port) PTE6 input/output (port) PTE5 input/output (port) PTE4 input/output (port) PTE3 input/output (port) PTE2 input/output (port) PTE1 input/output (port)
Page 872 Section 22 Pin Function Controller (PFC) Port Port Function (Related Module) PTG13 input/output (port) PTG12 input/output (port) PTG11 input/output (port) PTG10 input/output (port) PTG9 input/output (port) PTG8 input/output (port) PTG7 input (port) PTG6 input (port) PTG5 input (port) PTG4 input (port) PTG3 input (port) PTG2 input (port) PTG1 input (port)
Page 873: Register Descriptions
Port Port Function (Related Module) PTJ12 input/output (port) PTJ11 input/output (port) PTJ10 input/output (port) PTJ9 input/output (port) PTJ8 input/output (port) PTJ7 input/output (port) PTJ6 input/output (port) PTJ5 input/output (port) PTJ4 input/output (port) PTJ3 input/output (port) PTJ2 input/output (port) PTJ1 input/output (port) PTJ0 input/output (port) 22.1 Register Descriptions...
Page 874: Port A Control Register (Pacr)
Section 22 Pin Function Controller (PFC) 22.1.1 Port A Control Register (PACR) PACR is a 32-bit readable/writable register that selects the pin functions. PACR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 875 Initial Bit Name Value PA3MD2 PA3MD1 PA2MD2 PA2MD1 PA1MD2 PA1MD1 PA0MD2 PA0MD1 Note: The initial function of the port A is port input after a power-on reset. When ROM with more than 256 kbytes is allocated to space0, strong pull-downs must be prepared on the user board to input 0 to the upper address bits of the ROM immediately after a power-on reset.
Page 876: Port B Control Register (Pbcr)
Section 22 Pin Function Controller (PFC) 22.1.2 Port B Control Register (PBCR) PBCR is a 32-bit readable/writable register that selects the pin functions. PBCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 877: Port C Control Register (Pccr)
22.1.3 Port C Control Register (PCCR) PCCR is a 32-bit readable/writable register that selects the pin functions. PCCR is initialized to H'0C000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 878: Port D Control Register (Pdcr)
Section 22 Pin Function Controller (PFC) Initial Bit Name Value PC3MD2 PC3MD1 PC2MD2 PC2MD1 PC1MD2 PC1MD1 PC0MD2 PC0MD1 22.1.4 Port D Control Register (PDCR) PDCR is a 32-bit readable/writable register that selects the pin functions. PDCR is initialized to H'00000000 (MD3 = 0, 16-bit bus width) or H'FFFFFFFF (MD3 = 1, 32-bit bus width) by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 879 Initial Bit Name Value PD8MD2 PD8MD1 PD7MD2 PD7MD1 PD6MD2 PD6MD1 PD5MD2 PD5MD1 PD4MD2 PD4MD1 PD3MD2 PD3MD1 PD2MD2 PD2MD1 PD1MD2 PD1MD1 PD0MD2 PD0MD1 Section 22 Pin Function Controller (PFC) Description PDn Mode 2 and 1 The combination of bits PDnMD2 and PDnMD1 (n = 0 to 15) controls the pin functions.
Page 880: Port E Control Register (Pecr)
Section 22 Pin Function Controller (PFC) 22.1.5 Port E Control Register (PECR) PECR is a 32-bit readable/writable register that selects the pin functions. PECR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 881 Initial Bit Name Value PE3MD2 PE3MD1 PE2MD2 PE2MD1 PE1MD2 PE1MD1 PE0MD2 PE0MD1 Section 22 Pin Function Controller (PFC) Description PEn Mode 2 and 1 The combination of bits PEnMD2 and PEnMD1 (n = 0 to 15) controls the pin functions. 00: Port input 01: Port output 10: Reserved (When set, correct operation cannot be...
Page 882: Port E I/O Register (Peior)
Section 22 Pin Function Controller (PFC) 22.1.6 Port E I/O Register (PEIOR) PEIOR is a 16-bit readable/writable register that selects the input/output direction of the port E pins. The PE15IOR to PE0IOR bits correspond to the PE15/TIOC0A to PE0/TIOC4D pins. PEIOR is valid only when the port E pins function as the TIOC pins of the MTU (other functions).
Page 883: Port E Mtu R/W Enable Register (Pemturwer)
22.1.7 Port E MTU R/W Enable Register (PEMTURWER) PEMTURWER is a 16-bit readable/writable register that allows access of the MTU registers. PEMTURWER is initialized to H'0001 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode. Initial Bit Name Value...
Page 884: Port F Control Register (Pfcr)
Section 22 Pin Function Controller (PFC) 22.1.8 Port F Control Register (PFCR) PFCR is a 32-bit readable/writable register that selects the pin functions. PFCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 885 Initial Bit Name Value PF7MD2 PF7MD2 PF6MD2 PF6MD2 PF5MD2 PF5MD2 PF4MD2 PF4MD2 PF3MD2 PF3MD2 PF2MD2 PF2MD2 PF1MD2 PF1MD2 PF0MD2 PF0MD2 Section 22 Pin Function Controller (PFC) Description PFn Mode 2,1 The combination of bits PFnMD2 and PFnMD1 controls the pin functions. (n = 0 to 7) Port input Port output 10, 11: Reserved (When set, correct operation cannot...
Page 886: Port G Control Register
Section 22 Pin Function Controller (PFC) 22.1.9 Port G Control Register (PGCR) PGCR is a 32-bit readable/writable register that selects the pin functions. PGCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in the standby mode, or in the sleep mode.
Page 887 Initial Bit Name Value PG7MD2 PG7MD2 PG6MD2 PG6MD2 PG5MD2 PG5MD2 PG4MD2 PG4MD2 PG3MD2 PG3MD2 PG2MD2 PG2MD2 PG1MD2 PG1MD2 PG0MD2 PG0MD2 Note: There is no bit for changing the function of port G (pins ANn: analog inputs for the A/D converter) between input and other functions because the function returns to input on completion of A/D conversion.
Page 888: Port H Control Register (Phcr)
Section 22 Pin Function Controller (PFC) 22.1.10 Port H Control Register (PHCR) PHCR is a 32-bit readable/writable register that selects the pin functions. PHCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 889: Port J Control Register (Pjcr)
Initial Bit Name Value PH3MD2 PH3MD2 PH2MD2 PH2MD2 PH1MD2 PH1MD2 PH0MD2 PH0MD2 22.1.11 Port J Control Register (PJCR) PJCR is a 32-bit readable/writable register that selects the pin functions. PJCR is initialized to H'00000000 by a power-on reset, and it is not initialized by a manual reset, in standby mode, or in sleep mode.
Page 890 Section 22 Pin Function Controller (PFC) Initial Bit Name Value PJ6MD2 PJ6MD2 PJ5MD2 PJ5MD2 PJ4MD2 PJ4MD2 PJ3MD2 PJ3MD2 PJ2MD2 PJ2MD2 PJ1MD2 PJ1MD2 PJ0MD2 PJ0MD2 Rev. 4.00 Sep. 14, 2005 Page 840 of 982 REJ09B0023-0400 Description PJn Mode 2 and 1 The combination of bits PJnMD2 and PJnMD1controls the pin functions.
Page 891: I/O Buffer Internal Block Diagram
22.2 I/O Buffer Internal Block Diagram 22.2.1 I/O Buffer with Weak Keeper All the I/O buffers except PTG10, PTG9, and PTG 7 to PTG 0 (IIC2 and analog pins) listed in table 22.1 have weak keepers that consist of two inverters to keep the status of the pin. Figure 22.1 shows the internal block diagram of the I/O buffer.
Page 892: Notes On Usage
Section 22 Pin Function Controller (PFC) SDA input data SCL input data SDA output data SCL output data PTG[10] output enable PTG[9] output enable PTG[10] output data PTG[9] output data PTG[10] input data PTG[9] input data Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain 22.3 Notes on Usage •...
Page 893: Section 23 I/O Ports
This LSI has nine 16-bit ports (ports A to J). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions). Each port has a data register which stores data for the pins. 23.1 Port A Port A is a 15-bit input/output port with the pin configuration shown in figure 23.1.
Page 894: Port A Data Register (Padr)
Section 23 I/O Ports 23.1.2 Port A Data Register (PADR) PADR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTA14 to PTA0. PADR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode or in sleep mode.
Page 895: Port B
Table 23.1 Port A Data Register (PADR) Read/Write Operations PAnMD2 PAnMD1 Pin Function Input Output Reserved Other functions Pin state (n = 0 to 14) 23.2 Port B Port B is a 9-bit input/output port with the pin configuration shown in figure 23.2. Each pin is controlled by the port B control register (PBCR) in the PFC.
Page 896: Port B Data Register (Pbdr)
Section 23 I/O Ports 23.2.2 Port B Data Register (PBDR) PBDR is a 9-bit readable/writable register with seven reserved bits that stores data for pins PTB8 to PTB0. PBDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Page 897: Port C
23.3 Port C Port C is a 16-bit input/output port with the pin configuration shown in figure 23.3. Each pin is controlled by the port C control register (PCCR) in the PFC. Port C 23.3.1 Register Description Port C has the following register. •...
Page 898: Port C Data Register (Pcdr)
Section 23 I/O Ports 23.3.2 Port C Data Register (PCDR) PCDR is a 16-bit readable/writable register that stores data for pins PTC15 to PTC0. PCDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Page 899: Port D
Table 23.3 Port C Data Register (PCDR) Read/Write Operations PCnMD2 PCnMD1 Pin State Input Output Reserved Other functions Pin state (n = 0 to 15) 23.4 Port D Port D comprises a 16-bit input/output port with the pin configuration shown in figure 23.4. Each pin is controlled by the port D control register (PDCR) in the PFC.
Page 900: Register Description
Section 23 I/O Ports 23.4.1 Register Description Port D has the following register. • Port D data register (PDDR) 23.4.2 Port D Data Register (PDDR) PDDR is a 16-bit readable/writable register that stores data for pins PTD15 to PTD0. PDDR is initialized to H'0000 by a power-on reset, after which the general input port function is set as the initial pin function, and the corresponding pin levels are read when MD3 = 0 (16-bit bus width in CS0 space) is set.
Page 901: Port E
Table 23.4 Port D Data Register (PDDR) Read/Write Operations PDnMD2 PDnMD1 Pin State Input Output Reserved Other function Pin state (n = 0 to 15) 23.5 Port E Port E is a 16-bit input/output port with the pin configuration shown in figure 23.5. Each pin is controlled by the port E control register (PECR) in the PFC.
Page 902: Register Description
Section 23 I/O Ports 23.5.1 Register Description Port E has the following register. • Port E data register (PEDR) 23.5.2 Port E Data Register (PEDR) PEDR is a 16-bit readable/writable register that stores data for pins PTE15 to PTE0. The PEDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Page 903: Port F
Table 23.5 Port E Data Register (PEDR) Read/Write Operations PEnMD2 PEnMD1 Pin State Input Output Reserved Other function Pin state (n = 0 to 15) 23.6 Port F Port F is a 16-bit input port with the pin configuration shown in figure 23.6. Each pin is controlled by the port F control register (PFCR) in the PFC.
Page 904: Register Description
Section 23 I/O Ports 23.6.1 Register Description Port F has the following register. • Port F data register (PFDR) 23.6.2 Port F Data Register (PFDR) PFDR is a 16-bit readable/writable register that stores data for pins PTF15 to PTF0. PFDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Page 905: Table 23.6 Port F Data Register (Pfdr) Read/Write Operations (Pf15Dt To Pf8Dt)
Table 23.6 Port F Data Register (PFDR) Read/Write Operations (PF15DT to PF8DT) PFnMD2 PFnMD1 Pin State Input Output Reserved Other function Pin state (n = 8 to 15) Table 23.7 Port F Data Register (PFDR) Read/Write Operations (PF7DT to PF0DT) PFnMD2 PFnMD1 Pin State Input Output...
Page 906: Port G
Section 23 I/O Ports 23.7 Port G Port G comprises a 6-bit input/output port and an 8-bit input port with the pin configuration shown in figure 23.7. Each pin is controlled by the port G control register (PGCR) in the PFC. Port G 23.7.1 Register Description...
Page 907: Port G Data Register
23.7.2 Port G Data Register (PGDR) PGDR a register that includes six readable/writable and eight readable bits with two reserved bits that store data for pins PTG13 to PTG0. PGDR13 to PGDR8 are initialized to H'00 by a power-on reset, but they retain their previous values by a manual reset, in standby mode, or in sleep mode.
Page 908: Table 23.8 Port G Data Register (Pgdr) Read/Write Operations (Pg13Dt To Pg11Dt, Pg8Dt)
Section 23 I/O Ports Table 23.8 Port G Data Register (PGDR) Read/Write Operations (PG13DT to PG11DT, PG8DT) PGnMD2 PGnMD1 Pin State Input Output Other than above Reserved (n = 8, 11 to 13) Table 23.9 Port G Data Register (PGDR) Read/Write Operations (PG10DT to PG9DT) PGnMD2 PGnMD1 Pin State Input Output...
Page 909: Port G Internal Block Diagram
Section 23 I/O Ports 23.7.3 Port G Internal Block Diagram Pins PTG7 to PTG0 are multiplexed with the A/D converter. (See section 22, Pin Function Controller (PFC).) The statuses of these pins are read only when the PGDR is read, but are always input to the A/D converter.
Page 910: Port H
Section 23 I/O Ports 23.8 Port H Port H comprises a 15-bit input/output port with the pin configuration shown in figure 23.9. Each pin is controlled by the port H control register (PHCR) in the PFC. Port H 23.8.1 Register Description Port H has the following register.
Page 911: Port H Data Register (Phdr)
23.8.2 Port H Data Register (PHDR) PHDR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTH14 to PTH0. PHDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Page 912: Port J
Section 23 I/O Ports Table 23.11 Port H Data Register (PHDR) Read/Write Operations PHnMD2 PHnMD1 Pin State Input Output Reserved Other functions Pin state (n = 0 to 14) 23.9 Port J Port J is a 13-bit input/output port with the pin configuration shown in figure 23.10. Each pin is controlled by the port J control register (PJCR) in the PFC.
Page 913: Port J Data Register (Pjdr)
23.9.2 Port J Data Register (PJDR) PJDR is a 13-bit readable/writable register with three reserved bits that stores data for pins PTJ12 to PTJ0. The PJDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in standby mode, or in sleep mode.
Page 914 Section 23 I/O Ports Rev. 4.00 Sep. 14, 2005 Page 864 of 982 REJ09B0023-0400...
Page 915: Section 24 List Of Registers
Section 24 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) • Descriptions by functional module, in order of the corresponding section numbers Entries that consist of - lines are for separation of the functional modules.
Page 916: Register Addresses
Section 24 List of Registers 24.1 Register Addresses corresponding section numbers) Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. Register Name Frequency control register —...
Page 917 Register Name Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 2 Interrupt mask register 4 Interrupt mask register 5 Interrupt mask register 6 Interrupt mask register 7 Interrupt mask register 8 Interrupt mask register 9 Interrupt mask register 10 Interrupt mask clear register 0 Interrupt mask clear register 1 Interrupt mask clear register 2...
Page 918 Section 24 List of Registers Register Name Break data register B Break data mask register B Break control register Execution Times Break Register Break address register B Break address mask register B Break bus cycle register B Branch source register Break address register A Break address mask register A Break bus cycle register A...
Page 919 Register Name Refresh timer control/status register Refresh timer counter Refresh time constant register Reset wait counter — DMA source address register_0 DMA destination address register_0 DMA transfer count register_0 DMA channel control register_0 DMA source address register_1 DMA destination address register_1 DMA transfer count register_1 DMA channel control register _1 DMA source address register_2...
Page 920 Section 24 List of Registers Register Name C bus control register 1 C bus control register 2 C bus mode register C bus interrupt enable register C bus status register C bus slave address register C bus transmit data register C bus receive data register NF2CYC register —...
Page 921 Register Name Timer output control register Timer gate control register Timer counter_3 Timer counter_4 Timer cycle data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer subcounter Timer cycle buffer register Timer general register C_3 Timer general register D_3...
Page 922 Section 24 List of Registers Register Name Timer control register_1 Timer mode register_1 Timer I/O control register _1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2...
Page 923 Register Name Bit rate register_1 Serial control register_1 Transmit FIFO data register_1 Serial status register_1 Receive FIFO data register_1 FIFO control register_1 FIFO data count register_1 Serial port register_1 Line status register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit FIFO data register_2 Serial status register_2 Receive FIFO data register_2...
Page 924 Section 24 List of Registers Register Name USB interrupt enable register 1 USBEP1 receive data size register USB interrupt select register 1 USB DMA transfer setting register USBEP3 data register USBEP1 data register USBEP2 data register USB transceiver control register USB interrupt flag register 2 USB interrupt enable register 2 USB bus power control register...
Page 925 Register Name Port J control register Port E I/O register Port E MTU R/W enable register — Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port J data register...
Page 926: Register Bits
Section 24 List of Registers 24.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation 31/23/15/7 30/22/14/6...
Page 927 Register Abbreviation 31/23/15/7 30/22/14/6 EXPEVT — — — — — — IPRF IPR15 IPR14 IPR7 IPR6 IPRG IPR15 IPR14 IPR7 IPR6 IPRH IPR15 IPR14 IPR7 IPR6 IPRI IPR15 IPR14 IPR7 IPR6 IMR0 IMR1 IMR2 IMR4 IMR5 IMR6 IMR7 IMR8 IMR9 IMR10 IMCR0 IMC7...
Page 928 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 IMCR9 IMC7 IMC6 IMCR10 IMC7 IMC6 IRR0 IRQ7R IRQ6R ICR1 — IRQE IRQ31S IRQ30S ICR3 — — — — IPRC IPR15 IPR14 IPR7 IPR6 IPRD IPR15 IPR14 IPR7 IPR6 IPRE IPR15 IPR14 IPR7 IPR6...
Page 929 Register Abbreviation 31/23/15/7 30/22/14/6 BETR — — BET7 BET6 BARB BAB31 BAB30 BAB23 BAB22 BAB15 BAB14 BAB7 BAB6 BAMRB BAMB31 BAMB30 BAMB23 BAMB22 BAMB15 BAMB14 BAMB7 BAMB6 BBRB — — CDB1 CDB0 BRSR — BSA23 BSA22 BSA15 BSA14 BSA7 BSA6 BARA BAA31 BAA30...
Page 930 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 CMNCR — — — — WAITSEL — DMAIW1 DMAIW0 CS0BCR — IWW2 IWRWS1 IWRWS0 — TYPE2 — — CS2BCR — IWW2 IWRWS1 IWRWS0 — TYPE2 — — CS3BCR — IWW2 IWRWS1 IWRWS0 —...
Page 931 Register Abbreviation 31/23/15/7 30/22/14/6 CS6ABCR — IWW2 IWRWS1 IWRWS0 — TYPE2 — — CS6BBCR — IWW2 IWRWS1 IWRWS0 — TYPE2 — — CS0WCR* — — — — — — CS0WCR* — — — — — — CS0WCR* — — — —...
Page 932 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 CS3WCR* — — — — — — CS3WCR* — — — — — WTRP1 A3CL0 — CS4WCR* — — — — — — CS4WCR* — — — — — — CS5AWCR* —...
Page 933 Register Abbreviation 31/23/15/7 30/22/14/6 CS6BWCR* — — — — — — CS6BWCR* — — — — — — SDCR — — — — — — — — RTCSR — — — RTCNT — — RTCOR — — RWTCNT — — —...
Page 934 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 DMATCR_0 CHCR_0 — SAR_1 DAR_1 DMATCR_1 CHCR_1 — — SAR_2 Rev. 4.00 Sep. 14, 2005 Page 884 of 982 REJ09B0023-0400 29/21/13/5 28/20/12/4 27/19/11/3 — — — — — — — — —...
Page 935 Register Abbreviation 31/23/15/7 30/22/14/6 DAR_2 DMATCR_2 CHCR_2 — — — — — SAR_3 DAR_3 DMATCR_3 CHCR_3 — — — — — 29/21/13/5 28/20/12/4 27/19/11/3 — — — — — — — — — — — — Section 24 List of Registers 26/18/10/2 25/17/9/1 24/16/8/0...
Page 936 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 DMAOR — — — — — — — — DMARS0 C1MID5 C1MID4 C0MID5 C0MID4 DMARS1 C3MID5 C3MID4 C2MID5 C2MID4 SDIR — — SDIDH DID31 DID30 DID23 DID22 SDIDL DID15 DID14 DID7 DID6 ICCR1 RCVD...
Page 937 Register Abbreviation 31/23/15/7 30/22/14/6 CMSTR_1 — — — — CMCSR_1 — — — CMCNT_1 CMCOR_1 TCR_3 CCLR2 CCLR1 TCR_4 CCLR2 CCLR1 TMDR_3 — — TMDR_4 — — TIORH_3 IOB3 IOB2 TIORL_3 IOD3 IOD2 TIORH_4 IOB3 IOB2 TIORL_4 IOD3 IOD2 TIER_3 TTGE TGFASEL —...
Page 938 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TCFD — TSR_4 TCFD — TSTR CST4 CST3 TSYR SYNC4 SYNC3 TCR_0 CCLR2 CCLR1 TMDR_0 — — TIORH_0 IOB3 IOB2 TIORL_0 IOD3 IOD2 TIER_0...
Page 939 Register Abbreviation 31/23/15/7 30/22/14/6 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 CCLR2 CCLR1 TMDR_1 — — TIOR_1 IOB3 IOB2 TIER_1 TTGE TGFASEL TCIEU TSR_1 TCFD — TCNT_1 TGRA_1 TGRB_1 TCR_2 CCLR2 CCLR1 TMDR_2 — — TIOR_2 IOB3 IOB2 TIER_2 TTGE TGFASEL TCIEU TSR_2 TCFD —...
Page 940 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 ICSR1 POE3F POE2F POE3M1 POE3M0 OCSR — — — SCSMR_0 — — SCBRR_0 SCSCR_0 — — SCFTDR_0 SCFSR_0 PER3 PER2 TEND SCFRDR_0 SCFCR_0 — — RTRG1 RTRG0 SCFDR_0 — — — —...
Page 941 Register Abbreviation 31/23/15/7 30/22/14/6 SCFCR_1 — — RTRG1 RTRG0 SCFDR_1 — — — — SCSPTR_1 — — RTSIO RTSDT SCLSR_1 — — — — SCSMR_2 — — SCBRR_2 SCSCR_2 — — SCFTDR_2 SCFSR_2 PER3 PER2 TEND SCFRDR_2 SCFCR2 — — RTRG1 RTRG0 SCFDR2...
Page 942 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 USBEPSZ0o — — USBEPDR0s D7 USBDASTS — — USBISR0 BRST EP1FULL USBEPSTL — — USBIER0 BRST EP1FULL USBIER1 — — USBEPSZ1 — — USBISR1 — — USBDMAR — — USBEPDR3 USBEPDR1 USBEPDR2 USBXVERCR —...
Page 943 Register Abbreviation 31/23/15/7 30/22/14/6 ADDRD1 ADCSR0 ADIE CKS1 CKS0 ADCSR1 ADIE CKS1 CKS0 ADCR DSMP — — — PACR — — PA11MD2 PA11MD1 PA10MD2 PA10MD1 PA9MD2 PA7MD2 PA7MD1 PA3MD2 PA3MD1 PBCR — — — — PB7MD2 PB7MD1 PB3MD2 PB3MD1 PCCR PC15MD2 PC15MD1 PC14MD2 PC14MD1 PC13MD2 PC13MD1 PC12MD2 PC12MD1 PC11MD2 PC11MD1 PC10MD2 PC10MD1 PC9MD2 PC7MD2...
Page 944 Section 24 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 PFCR PF15MD2 PF15MD1 PF11MD2 PF11MD1 PF7MD2 PF7MD1 PF3MD2 PF3MD1 PGCR — — PG11MD2 PG11MD1 PG10MD2 PG10MD1 PG9MD2 PG7MD2 PG7MD1 PG3MD2 PG3MD1 PHCR — — PH11MD2 PH11MD1 PH10MD2 PH10MD1 PH9MD2 PH7MD2 PH7MD1 PH3MD2 PH3MD1 PJCR...
Page 945 Register Abbreviation 31/23/15/7 30/22/14/6 PFDR PF15DT PF14DT PF7DT PF6DT PGDR — — PG7DT PG6DT PHDR — PH14DT PH7DT PH6DT PJDR — — PJ7DT PJ6DT Notes: 1. When the following memory is in use: normal memory, byte-selection SRAM, or MPX- IO (address/data multiplexed I/O) When burst ROM (asynchronous) is in use When burst ROM (synchronous) is in use When SDRAM is in use...
Page 946: Register States In Each Operating Mode
Section 24 List of Registers 24.3 Register States in Each Operating Mode Register Abbreviation Power-On Reset Manual Reset FRQCR Initialized* Retained WTCNT Initialized* Retained WTCSR Initialized* Retained STBCR Initialized Retained STBCR2 Initialized Retained STBCR3 Initialized Retained STBCR4 Initialized Retained CCR1 Initialized Initialized CCR2...
Page 947 Register Abbreviation Power-On Reset Manual Reset IMCR0 Initialized Initialized IMCR1 Initialized Initialized IMCR2 Initialized Initialized IMCR4 Initialized Initialized IMCR5 Initialized Initialized IMCR6 Initialized Initialized IMCR7 Initialized Initialized IMCR8 Initialized Initialized IMCR9 Initialized Initialized IMCR10 Initialized Initialized IRR0 Initialized Initialized ICR1 Initialized Initialized ICR3...
Page 948 Section 24 List of Registers Register Abbreviation Power-On Reset Manual Reset BBRA Initialized Retained BRDR Undefined* Retained CMNCR Initialized Retained CS0BCR Initialized Retained CS2BCR Initialized Retained CS3BCR Initialized Retained CS4BCR Initialized Retained CS5ABCR Initialized Retained CS5BBCR Initialized Retained CS6ABCR Initialized Retained CS6BBCR Initialized...
Page 949 Register Abbreviation Power-On Reset Manual Reset DAR_1 Undefined Undefined DMATCR_1 Undefined Undefined CHCR_1 Initialized Initialized SAR_2 Undefined Undefined DAR_2 Undefined Undefined DMATCR_2 Undefined Undefined CHCR_2 Initialized Initialized SAR_3 Undefined Undefined DAR_3 Undefined Undefined DMATCR_3 Undefined Undefined CHCR_3 Initialized Initialized DMAOR Initialized Initialized DMARS0...
Page 950 Section 24 List of Registers Register Abbreviation Power-On Reset Manual Reset CMCOR_0 Initialized Retained CMSTR_1 Initialized Retained CMCSR_1 Initialized Retained CMCNT_1 Initialized Retained CMCOR_1 Initialized Retained TCR_3 Initialized Retained TCR_4 Initialized Retained TMDR_3 Initialized Retained TMDR_4 Initialized Retained TIORH_3 Initialized Retained TIORL_3 Initialized...
Page 951 Register Abbreviation Power-On Reset Manual Reset TGRD_3 Initialized Retained TGRC_4 Initialized Retained TGRD_4 Initialized Retained TSR_3 Initialized Retained TSR_4 Initialized Retained TSTR Initialized Retained TSYR Initialized Retained TCR_0 Initialized Retained TMDR_0 Initialized Retained TIORH_0 Initialized Retained TIORL_0 Initialized Retained TIER_0 Initialized Retained TSR_0...
Page 952 Section 24 List of Registers Register Abbreviation Power-On Reset Manual Reset TIER_2 Initialized Retained TSR_2 Initialized Retained TCNT_2 Initialized Retained TGRA_2 Initialized Retained TGRB_2 Initialized Retained ICSR1 Initialized Retained OCSR Initialized Retained SCSMR_0 Initialized Retained SCBRR_0 Initialized Retained SCSCR_0 Initialized Retained SCFTDR_0 Undefined...
Page 953 Register Abbreviation Power-On Reset Manual Reset SCSCR_2 Initialized Retained SCFTDR_2 Undefined Retained SCFSR_2 Initialized Retained SCFRDR_2 Undefined Retained SCFCR_2 Initialized Retained SCFDR_2 Initialized Retained SCSPTR_2 Initialized Retained SCLSR_2 Initialized Retained USBIFR0 Initialized Retained USBIFR1 Initialized Retained USBEPDR0i Undefined Retained USBEPDR0o Undefined Retained USBTRG...
Page 954 Section 24 List of Registers Register Abbreviation Power-On Reset Manual Reset USBIER2 Initialized Retained USBCTRL Initialized Retained ADDRA0 Initialized Retained ADDRB0 Initialized Retained ADDRC0 Initialized Retained ADDRD0 Initialized Retained ADDRA1 Initialized Retained ADDRB1 Initialized Retained ADDRC1 Initialized Retained ADDRD1 Initialized Retained ADCSR0 Initialized...
Page 955 Register Abbreviation Power-On Reset Manual Reset PFDR Initialized Retained PGDR Initialized* Retained PHDR Initialized Retained PJDR Initialized Retained Notes: 1. Not initialized by a power-on reset. 2. Some bits are initialized. 3. Some bits are not initialized. 4. Initialized by TRST assertion or when the TAP controller is in the test-logic-reset state. Software Standby Module Standby Sleep...
Page 956 Section 24 List of Registers Rev. 4.00 Sep. 14, 2005 Page 906 of 982 REJ09B0023-0400...
Page 957: Section 25 Electrical Characteristics
Section 25 Electrical Characteristics The specifications shown in this section are preliminary. After the characteristics have been evaluated, the specifications may be changed without notice. 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Power supply voltage (Internal)
Page 958: Power-On Sequence
Section 25 Electrical Characteristics 25.1.1 Power-On Sequence Supply the power so that VccQ (3.3-V system) and Vcc (1.8-V system) are supplied simultaneously or Vcc is supplied after VccQ is supplied. Recommended values for the power-on procedure are shown below. Unsettling opration Clock starts oscillation The time at which VccQ reaches V...
Page 959: Table 25.2 Recommended Values For Power-On/Off Sequence
Table 25.2 Recommended Values for Power-On/Off Sequence Item Time lag between VccQ and Vcc when turning on tpwu Time lag between VccQ and Vcc when turning off tpwd Unsettling operation time Notes: 1. The figures shown above are recommended values, so they represent guidelines rather than strict requirements.
Page 960: Dc Characteristics
Section 25 Electrical Characteristics 25.2 DC Characteristics Tables 25.3 and 25.4 list DC characteristics. Table 25.3 DC Characteristics (1) [Common Items] Conditions: Ta = −40°C to +85°C Item Current Normal operation consumption* Standby mode Sleep mode Input leakage All input pins current Three-state All input/output pins,...
Page 961: Table 25.3 Dc Characteristics (4) [Usb-Related Pins]
Table 25.3 DC Characteristics (2) [Except for I (PLL1, PLL2) = 1.8 V ±5%, V Conditions: V V, V (PLL1, PLL2) = AV Item Power supply RESETP, RESETM, Input high NMI, MD3, MD2 voltage MD0, ASEMD0, TRST EXTAL, CKIO Ports G7 to G0 Input pins other than above (excluding Schmitt pins)
Page 962 Section 25 Electrical Characteristics Item Schmitt trigger TIOC0A to TIOC0D, input TIOC1A, TIOC1B, characteristics TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TCLKA to TCLKD, SCK0 to SCK2, RxD0 to RxD2, CTS0 to CTS2, IRQ7 to IRQ0 Output high All output pins voltage Output low PE0 to PE4, PE6...
Page 963: Table 25.3 Dc Characteristics (2) [Except For I C- And Usb-Related Pins]
Table 25.3 DC Characteristics (3) [I Conditions: V Q = 3.0 V to 3.6 V, V Item Power supply Input high voltage Input low voltage Schmitt trigger input characteristics Output low voltage Note: The SCL and SDA pins (open-drain pins) When the port functions are selected as the general inputs or outputs, however, these pins have the usual V Table 25.3 DC Characteristics (4) [USB-Related Pins*]...
Page 964: Table 25.3 Dc Characteristics (5) [Usb Transceiver-Related Pins]
Section 25 Electrical Characteristics Table 25.3 DC Characteristics (5) [USB Transceiver-Related Pins*] Conditions: Ta = −40°C to +85°C Item Differential input sensitivity Differential common mode range Single ended receiver threshold voltage Output high voltage Output low voltage Tri-state leak current Note: The DP and DM pins Table 25.4 Permissible Output Currents...
Page 965: Ac Characteristics
25.3 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 25.5 Maximum Operating Frequency Q = 3.0 V to 3.6 V, V Conditions: V +85°C Item...
Page 966: Clock Timing
Section 25 Electrical Characteristics 25.3.1 Clock Timing Table 25.6 Clock Timing Q = 3.0 V to 3.6 V, V Conditions: V = 0 V, Ta = −40°C to +85°C Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input pulse low width EXTAL clock input pulse high width EXTAL clock input rising time EXTAL clock falling time...
Page 967: Figure 25.2 Extal Clock Input Timing
EXTAL* (input) 1/2 V Note: * When the clock is input on the EXTAL pin. Figure 25.2 EXTAL Clock Input Timing CKIH CKIO (input) 1/2 V Figure 25.3 CKIO Clock Input Timing CKOH CKIO, CKIO2 (output) 1/2V Figure 25.4 CKIO and CKIO2 Clock Input Timing Section 25 Electrical Characteristics EXcyc 1/2 V...
Page 968: Figure 25.5 Oscillation Settling Timing (Power-On)
Section 25 Electrical Characteristics CKIO, Internal clock RESETP RESETM Note: Oscillation settling time when the internal oscillator is used. Figure 25.5 Oscillation Settling Timing (Power-On) Figure 25.6 Phase Difference between CKIO and CKIO2 Standby period CKIO, Internal clock RESETP RESETM Note: Oscillation settling time when the internal oscillator is used.
Page 969: Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled By Nmi Or Irq)
Section 25 Electrical Characteristics Standby period Oscillation settling time CKIO, Internal clock OSC3 NMI, IRQ Note: Oscillation settling time when the internal oscillator is used. Figure 25.8 Oscillation Settling Timing (Standby Mode Canceled by NMI or IRQ) Rev. 4.00 Sep. 14, 2005 Page 919 of 982 REJ09B0023-0400...
Page 970: Control Signal Timing
Section 25 Electrical Characteristics 25.3.2 Control Signal Timing Table 25.7 Control Signal Timing Q = 3.0 V to 3.6 V, V Conditions: V = 0 V, Ta = −40°C to +85°C Item RESETP pulse width RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time...
Page 971: Figure 25.9 Reset Input Timing
CKIO RESPS/MS RESETP RESETM Figure 25.9 Reset Input Timing CKIO RESETP RESETM IRQ7 to IRQ0 Figure 25.10 Interrupt Input Timing Section 25 Electrical Characteristics RESPS/MS RESPW/MW RESPH/MH RESPS/MS NMIH NMIS IRQH IRQS Rev. 4.00 Sep. 14, 2005 Page 921 of 982 REJ09B0023-0400...
Page 972: Figure 25.11 Bus Release Timing
Section 25 Electrical Characteristics CKIO (HIZCNT = 0) CKIO (HIZCNT = 1) BREQH BREQS BREQ BACK A25 to A0, D31 to D0 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, CKE Normal mode CKIO input STATUS 0 STATUS 1 RD, RD/WR, RASU/L, CASU/L, CSn, WEn,...
Page 973: Ac Bus Timing
25.3.3 AC Bus Timing Table 25.8 Bus Timing Conditions: Clock mode 2/6/7, V Item Address delay time 1 Address delay time 2 Address delay time 3 Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read write delay time 1 Read write delay time 2 Read strobe delay time...
Page 974 Section 25 Electrical Characteristics Item Write data delay time 1 Write data delay time 2 Write data delay time 3 Write enable hold time 1 Write enable hold time 2 Write enable hold time 3 WAIT setup time 1 WAIT setup time 2 WAIT hold time 1 WAIT hold time 2 RAS delay time 1...
Page 975: Basic Timing
25.3.4 Basic Timing A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 DACKn* Note: * Waveform for DACKn when active low is selected. Figure 25.13 Basic Bus Timing for Normal Space (No Wait) CKIO CSD1 RWD1 WED1 WDD1 DACD Section 25 Electrical Characteristics...
Page 976: Figure 25.14 Basic Bus Timing For Normal Space (Software 1 Wait)
Section 25 Electrical Characteristics CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 DACKn* WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.14 Basic Bus Timing for Normal Space (Software 1 Wait) Rev.
Page 977: Figure 25.15 Basic Bus Timing For Normal Space (One Cycle Of Externally Input/Waitsel = 0)
CKIO A25 to A0 CSD1 RWD1 RD/WR Read D31 to D0 WED1 Write WDD1 D31 to D0 DACD DACKn* WTH1 WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.15 Basic Bus Timing for Normal Space (One Cycle of Externally Input/WAITSEL = 0) Section 25 Electrical Characteristics RDS1 WED1...
Page 978: Figure 25.16 Basic Bus Timing For Normal Space (One Cycle Of Externally Input/Waitsel = 1)
Section 25 Electrical Characteristics CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 DACKn* WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.16 Basic Bus Timing for Normal Space (One Cycle of Externally Input/WAITSEL = 1) Rev.
Page 979: Figure 25.17 Basic Bus Timing For Normal Space (One Cycle Of Software Wait, External Wait Cycle Valid (Wm Bit = 0), No Idle Cycle)
CKIO A25 to A0 CSD1 RWD1 RD/WR Read D15 to D0 WED1 Write WDD1 D15 to D0 DACD DACKn* WAIT Note: * Waveform for DACKn when active low is selected. Figure 25.17 Basic Bus Timing for Normal Space (One Cycle of Software Wait, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle) Section 25 Electrical Characteristics CSD1 CSD1...
Page 980: Figure 25.18 Mpx-Io Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 CSD1 CS5B RWD1 RD/WR D15 to D0 WE1 to WE0 D15 to D0 WAIT DACD DACKn* Note: * Waveform for DACKn when active low is selected. Figure 25.18 MPX-IO Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) Rev.
Page 981: Figure 25.19 Burst Mpx-Io Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait)
CKIO A25 to A0 CSD1 CS6B RWD1 RD/WR FRAME WDD1 Read D31 to D0 WDD1 Write D31 to D0 DACD DACKn, TENDn* WAIT Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.19 Burst MPX-IO Interface Bus Cycle Single Read Write (One Address Cycle, One Software Wait) Section 25 Electrical Characteristics Tmd1w...
Page 982: Bus Cycle Of Byte-Selection Sram
Section 25 Electrical Characteristics 25.3.5 Bus Cycle of Byte-Selection SRAM CKIO A25 to A0 RD/WR Read D31 to D0 RD/WR Write D31 to D0 DACKn, TENDn* WAIT Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control)) Rev.
Page 983: Figure 25.21 Byte-Selection Sram Bus Cycle (Sw = 1 Cycle, Hw = 1 Cycle, One Asynchronous External Wait Cycle, Bas = 1 (Write Cycle We Control))
CKIO A25 to A0 WED2 RD/WR Read D31 to D0 RD/WR WDD1 Write D31 to D0 DACKn, TENDn* WAIT Note: * Waveform for DACKn and TENDn when active low is selected. Figure 25.21 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control)) CSD1 RWD1...
Page 984: Burst Rom Read Cycle
Section 25 Electrical Characteristics 25.3.6 Burst ROM Read Cycle CKIO A25 to A0 CSD1 RWD1 RD/WR D31 to D0 DACD DACKn, TENDn* WAIT Note: * Waveform for DACKn and TENDn when active low is selected. (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst) Rev.
Page 985: Synchronous Dram Timing
25.3.7 Synchronous DRAM Timing CKIO A25 to A0 A12/A11* CSD1 RWD1 RD/WR RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle) Column address...
Page 986: Figure 25.24 Synchronous Dram Single Read Bus Cycle (Auto Precharge, Cas Latency 2, Wtrcd = 1 Cycle, Wtrp = 1 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 Row address A12/A11* CSD1 RWD1 RD/WR RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.24 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle) Rev.
Page 987: Figure 25.25 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, Cas Latency 2, Wtrcd = 0 Cycle, Wtrp = 1 Cycle)
CKIO A25 to A0 address Read command A12/A11* CSD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASU/L DQMD1 DQMxx D31 to D0 (High) DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle) Section 25 Electrical Characteristics...
Page 988: Figure 25.26 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, Cas Latency 2, Wtrcd = 1 Cycle, Wtrp = 0 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 address A12/A11* CSD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle) Rev.
Page 989: Figure 25.27 Synchronous Dram Single Write Bus Cycle (Auto Precharge, Trwl = 1 Cycle)
CKIO A25 to A0 address A12/A11* CSD1 RWD1 RD/WR RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) Section 25 Electrical Characteristics...
Page 990: Figure 25.28 Synchronous Dram Single Write Bus Cycle (Auto Precharge, Wtrcd = 2 Cycles, Trwl = 1 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 A12/A11* RD/WR RASU/L CASU/L DQMxx D31 to D0 DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) Rev.
Page 991: Figure 25.29 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, Wtrcd = 0 Cycle, Trwl = 1 Cycle)
CKIO A25 to A0 address A12/A11* CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASU/L DQMD1 DQMxx WDD2 D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) Section 25 Electrical Characteristics...
Page 992: Figure 25.30 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, Wtrcd = 1 Cycle, Trwl = 1 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 A12/A11* CSD1 RWD1 RD/WR RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) Rev.
Page 993: Figure 25.31 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: Act + Read Commands, Cas Latency 2, Wtrcd = 0 Cycle)
CKIO A25 to A0 address A12/A11* CSD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle) Column...
Page 994: Figure 25.32 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: Read Command, Same Row Address, Cas Latency 2, Wtrcd = 0 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 A12/A11* RD/WR RASU/L CASU/L DQMxx D31 to D0 DACKn* Note: Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle) Rev.
Page 995: Figure 25.33 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: Pre + Act + Read Commands, Different Row Addresses, Cas Latency 2, Wtrcd = 0 Cycle)
CKIO A25 to A0 address A12/A11* CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle)
Page 996: Figure 25.34 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: Act + Write Commands, Wtrcd = 0 Cycle, Trwl = 0 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 A12/A11* RD/WR RASU/L CASU/L DQMxx D31 to D0 DACKn* Note: Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle) Rev.
Page 997: Figure 25.35 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: Write Command, Same Row Address, Wtrcd = 0 Cycle, Trwl = 0 Cycle)
Tnop CKIO A25 to A0 A12/A11* CSD1 RWD1 RD/WR RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle, Section 25 Electrical Characteristics...
Page 998: Figure 25.36 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: Pre + Act + Write Commands, Different Row Addresses, Wtrcd = 0 Cycle, Trwl = 0 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 A12/A11* CSD1 RWD1 RD/WR RASD1 RASU/L CASU/L DQMD1 DQMxx D31 to D0 DACD DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, Rev.
Page 999: Figure 25.37 Synchronous Dram Auto-Refreshing Timing (Wtrp = 1 Cycle, Wtrc = 3 Cycles)
CKIO A25 to A0 A12/A11* CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASU/L DQMxx D31 to D0 DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3.
Page 1000: Figure 25.38 Synchronous Dram Self-Refreshing Timing (Wtrp = 1 Cycle)
Section 25 Electrical Characteristics CKIO A25 to A0 A12/A11* CSD1 RWD1 RD/WR RASD1 RASU/L CASU/L DQMxx D31 to D0 DACKn* Note: 1. An address pin to be connected to pin A10 of SDRAM. 2. Waveform for DACKn when active low is selected. 3.

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Sh7641

Renesas HD6417641 Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 DSP Operation

Section 4 Clock Pulse Generator (CPG)

Section 5 Watchdog Timer (WDT)

Section 6 Power-Down Modes

Section 7 Cache

Section 8 X/Y Memory

Section 9 Exception Handling

Section 10 Interrupt Controller (INTC)

Section 11 User Break Controller (UBC)

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Summary of Contents for Renesas HD6417641