Renesas HD6417641 Hardware Manual page 349

Bit Bit Name
1 HW1
0 HW0
• CS6BWCR
Bit Bit Name

31 to 21
20 BAS

19 to 13
12 SW1
11 SW0
Initial
Value R/W Description
Delay Cycles from RD, WEn Negation to Address,
0 R/W
CSn Negation
0 R/W
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Byte-Selection SRAM Byte Access Selection
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read/write access
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CSn Assertion
0 R/W
to RD, WEn Assertion
0 R/W
Specify the number of delay cycles from address, CSn
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Section 12 Bus State Controller (BSC)
asserts the RD/WR signal during the write access
cycle.
cycle and asserts the RD/WR signal at the write
timing.
Rev. 4.00 Sep. 14, 2005 Page 299 of 982
REJ09B0023-0400