Figure 25.36 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: Pre + Act + Write Commands, Different Row Addresses, Wtrcd = 0 Cycle, Trwl = 0 Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
t
AD1
A25 to A0
t
AD1
1
A12/A11*
t
CSD1
CSn
t
RWD1
RD/WR
t
RASD1
RASU/L
CASU/L
t
DQMD1
DQMxx
D31 to D0
BS
CKE
t
DACD
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
Rev. 4.00 Sep. 14, 2005 Page 948 of 982
REJ09B0023-0400
Tp Tpw Tr
Row address
t
AD1
t
RWD1
t t
RASD1 RASD1
WTRCD = 0 Cycle, TRWL = 0 Cycle)
Tc1 Tc2
t t t
AD1 AD1 AD1
Column
address
t
AD1
Writecommand
t
RWD1
t
RASD1
t
CASD1
t t
WDD2 WDH2
t
BSD
(High)
Tc3 Tc4
t t
AD1 AD1
t
AD1
t
CSD1
t
RWD1
t
CASD1
t
DQMD1
t t
WDD2 WDH2
t
BSD
t
DACD