Figure 25.30 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, Wtrcd = 1 Cycle, Trwl = 1 Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
t
A25 to A0
t
1
A12/A11*
t
CSn
t
RD/WR
t
RASU/L
CASU/L
t
DQMxx
D31 to D0
BS
CKE
DACKn*
2
Note:
Figure 25.30 Synchronous DRAM Burst Write Bus Cycle
(Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 942 of 982
REJ09B0023-0400
Tr Trw
t
AD1 AD1
Row
address
t
AD1 AD1
CSD1
t
RWD1
RWD1
t
RASD1 RASD1
t
CASD1
DQMD1
t
WDD2
t
BSD
(High)
t
DACD
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Tc1 Tc2 Tc3
t t
AD1 AD1
Column
address
WRIT command
t
WDH2
Tc4 Trwl
t t
AD1 AD1
t t
AD1 AD1
WriteA
command
t
CSD1
t
RWD1
t
CASD1
t
DQMD1
t t
WDD2 WDH2
t
BSD
t
DACD