Figure 25.33 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: Pre + Act + Read Commands, Different Row Addresses, Cas Latency 2, Wtrcd = 0 Cycle) - Renesas HD6417641 Hardware Manual

Tp
CKIO
t
AD1
A25 to A0
t
AD1
1
A12/A11*
t
CSD1
CSn
t
RWD1
RD/WR
t
RASD1
RASU/L
CASU/L
t
DQMD1
DQMxx
D31 to D0
BS
CKE
t
DACD
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
Trw Tr Tc1
t
AD1
Row
address
t t
AD1 AD1
t
RWD1
t t t
RASD1 RASD1 RASD1
t
CASD1
t
BSD
CAS Latency 2, WTRCD = 0 Cycle)
Section 25 Electrical Characteristics
Td1 Td2
Tc2 Tc3 Tc4
t t t
AD1 AD1 AD1
Column
address
Read command
t t
RDS2 RDH2
(High)
Rev. 4.00 Sep. 14, 2005 Page 945 of 982
Td3 Td4
Tde
t
CSD1
t
CASD1
t
DQMD1
t t
RDS2 RDH2
t
BSD
t
DACD
REJ09B0023-0400
t
AD1
t
AD1
t
RWD1