Table of Contents
Advertisement
Section 14 U Memory........................................................................................451
14.1 Features.............................................................................................................................. 451
14.2 U Memory Access from CPU ............................................................................................ 452
14.3 U Memory Access from DSP............................................................................................. 452
14.4 U Memory Access from DMAC ........................................................................................ 452
14.5 Usage Note......................................................................................................................... 453
14.6 Sleep Mode ........................................................................................................................ 453
14.7 Address Error ..................................................................................................................... 453
Section 15 User Debugging Interface (H-UDI) .................................................455
15.1 Features.............................................................................................................................. 455
15.2 Input/Output Pins ............................................................................................................... 456
15.3 Register Descriptions ......................................................................................................... 457
15.3.1 Bypass Register (SDBPR) .................................................................................... 457
15.3.2 Instruction Register (SDIR) .................................................................................. 457
15.3.3 Boundary Scan Register (SDBSR) ....................................................................... 458
15.3.4 ID Register (SDID)............................................................................................... 467
15.4 Operation ........................................................................................................................... 468
15.4.1 TAP Controller ..................................................................................................... 468
15.4.2 Reset Configuration .............................................................................................. 469
15.4.3 TDO Output Timing ............................................................................................. 469
15.4.4 H-UDI Reset ......................................................................................................... 470
15.4.5 H-UDI Interrupt .................................................................................................... 470
15.5 Boundary Scan ................................................................................................................... 471
15.5.1 Supported Instructions .......................................................................................... 471
15.5.2 Points for Attention............................................................................................... 472
15.6 Usage Notes ....................................................................................................................... 472
2
16.1 Features.............................................................................................................................. 473
16.2 Input/Output Pins ............................................................................................................... 475
16.3 Register Descriptions ......................................................................................................... 476
2
16.3.1 I
C Bus Control Register 1 (ICCR1)..................................................................... 476
2
16.3.2 I
C Bus Control Register 2 (ICCR2)..................................................................... 479
2
16.3.3 I
C Bus Mode Register (ICMR)............................................................................ 480
2
16.3.4 I
C Bus Interrupt Enable Register (ICIER) ........................................................... 482
2
16.3.5 I
C Bus Status Register (ICSR)............................................................................. 484
16.3.6 Slave Address Register (SAR).............................................................................. 486
2
16.3.7 I
C Bus Transmit Data Register (ICDRT)............................................................. 487
2
16.3.8 I
C Bus Receive Data Register (ICDRR).............................................................. 487
Rev. 4.00 Sep. 14, 2005 Page xix of l
Advertisement
Table of Contents
