(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted
in First Access = 2, Wait Cycles Inserted in Second and
Subsequent Accesses = 1)..................................................................................... 377
CS6BWCR.MPXMD = 0) .................................................................................... 385
CS6BWCR.MPXMD = 0) .................................................................................... 386
Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page xxxii of l