12.5 Operating Description........................................................................................................ 321
12.5.5 MPX-I/O Interface................................................................................................ 332
12.5.6 SDRAM Interface ................................................................................................. 335
12.5.12 Bus Arbitration ..................................................................................................... 399
12.5.13 Others.................................................................................................................... 401
13.1 Features.............................................................................................................................. 405
13.2 Input/Output Pins............................................................................................................... 407
13.3 Register Descriptions......................................................................................................... 408
13.4 Operation ........................................................................................................................... 424
13.4.1 DMA Transfer Flow ............................................................................................. 424
13.4.3 Channel Priority.................................................................................................... 429
13.4.7 Notes on Usage ..................................................................................................... 445
Rev. 4.00 Sep. 14, 2005 Page xviii of l