Renesas HD6417641 Hardware Manual page 31

Section 11 User Break Controller (UBC)
Figure 11.1 Block Diagram of User Break Controller................................................................ 242
Section 12 Bus State Controller (BSC)
Figure 12.1 BSC Functional Block Diagram.............................................................................. 271
Figure 12.2 Address Space ......................................................................................................... 274
Figure 12.3 Normal Space Basic Access Timing (Access Wait 0)............................................. 324
Figure 12.4 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access,
CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0) .................................... 325
Figure 12.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access,
CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0) .................................... 326
Figure 12.6 Example of 32-Bit Data-Width SRAM Connection ................................................ 327
Figure 12.7 Example of 16-Bit Data-Width SRAM Connection ................................................ 328
Figure 12.8 Example of 8-Bit Data-Width SRAM Connection .................................................. 328
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only) ............................... 329
Figure 12.10 Wait State Timing for Normal Space Access
(Wait State Insertion Using WAIT Signal) ........................................................... 330
Figure 12.11 CSn Assert Period Expansion................................................................................ 331
Figure 12.12 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait) . 332
Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) .... 333
Figure 12.14 Access Timing for MPX Space (Address Cycle Access Wait 1,
Data Cycle Wait 1, External Wait 1)..................................................................... 334
Figure 12.15 Example of 32-Bit Data Width SDRAM Connection
(RASU and CASU are Not Used)......................................................................... 336
Figure 12.16 Example of 16-Bit Data Width SDRAM Connection
(RASU and CASU are Not Used)......................................................................... 337
Figure 12.17 Example of 16-Bit Data Width SDRAM Connection
(RASU and CASU are Used)................................................................................ 338
Figure 12.18 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) ............................. 352
Figure 12.19 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD1 and
WTRCD0 = 1 Cycle, Auto Pre-Charge) ............................................................... 353
Figure 12.20 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge) ...................... 354
Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge) ................................................. 356
Figure 12.22 Single Write Basic Timing (Auto-Precharge) ........................................................ 357
Figure 12.23 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) .................... 359
Figure 12.24 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank,
CAS Latency 1)..................................................................................................... 360
Figure 12.25 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank,
CAS Latency 1)..................................................................................................... 361
Figure 12.26 Single Write Timing (Bank Active, Different Bank) ............................................ 362
Figure 12.27 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank)..... 363
Rev. 4.00 Sep. 14, 2005 Page xxxi of l