Table of Contents
Advertisement
6.2
Register Descriptions ......................................................................................................... 166
6.2.1
Standby Control Register (STBCR)...................................................................... 166
6.2.2
Standby Control Register 2 (STBCR2)................................................................. 167
6.2.3
Standby Control Register 3 (STBCR3)................................................................. 168
6.2.4
Standby Control Register 4 (STBCR4)................................................................. 170
6.3
Operation ........................................................................................................................... 171
6.3.1
Sleep Mode ........................................................................................................... 171
6.3.2
Standby Mode ....................................................................................................... 172
6.3.3
Module Standby Function..................................................................................... 174
6.3.4
STATUS Pin Change Timings.............................................................................. 174
Section 7 Cache .................................................................................................179
7.1
Features.............................................................................................................................. 179
7.1.1
Cache Structure..................................................................................................... 180
7.2
Register Descriptions ......................................................................................................... 182
7.2.1
Cache Control Register 1 (CCR1) ........................................................................ 182
7.2.2
Cache Control Register 2 (CCR2) ........................................................................ 183
7.3
Cache Operation................................................................................................................. 186
7.3.1
Searching Cache ................................................................................................... 186
7.3.2
Read Access.......................................................................................................... 188
7.3.3
Prefetch Operation ................................................................................................ 188
7.3.4
Write Access ......................................................................................................... 188
7.3.5
Write-Back Buffer ................................................................................................ 189
7.3.6
Coherency of Cache and External Memory .......................................................... 189
7.4
Memory-Mapped Cache .................................................................................................... 190
7.4.1
Address Array ....................................................................................................... 190
7.4.2
Data Array ............................................................................................................ 190
7.4.3
Usage Examples.................................................................................................... 192
Section 8 X/Y Memory......................................................................................193
8.1
Features.............................................................................................................................. 193
8.2
X/Y Memory Access from CPU ........................................................................................ 194
8.3
X/Y Memory Access from DSP......................................................................................... 194
8.4
X/Y Memory Access from DMAC .................................................................................... 195
8.5
Usage Note......................................................................................................................... 195
8.6
Sleep Mode ........................................................................................................................ 195
8.7
Address Error ..................................................................................................................... 195
Section 9 Exception Handling ...........................................................................197
9.1
Register Descriptions ......................................................................................................... 198
Rev. 4.00 Sep. 14, 2005 Page xv of l
Advertisement
Table of Contents
