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A.
I/O Port States in Each Processing State
Table A.1
I/O Port States in Each Processing State
MCU Operating
Mode
Port Name
Pin Name
EXPE Setting
Port 1
0 / 1 (DDR=0)
A7 to A0
1 (DDR=1)
Port 27 to 24 X
Port 23 to 20 0 / 1 (DDR=0)
A11 to A8
1 (DDR=1)
Port 3
0
D15 to D8
1
Port 47 to 44 0
A15 to A12
1
Port 43 to 40 0 / 1 (8 bits)
D7 to D4
1 (16 bits)
Port 57
0
WR, HWR
1
Port 56
0
EXCL
1 (DDR=0)
φ
1 (DDR=1)
Port 55 to 50 X
Port 67 to 64 X
Port 63 to 60 0 / 1 (8 bits)
D3 to D0
1 (16 bits)
Port 7
X
Port 8
X
Appendix
Hardware
Reset
Standby Mode
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Software
Standby Mode
Sleep Mode
kept
kept
kept*
kept*
kept
kept
kept
kept
kept*
kept*
kept
kept
T
T
kept
kept
kept*
kept*
kept
kept
T
T
kept
kept
H
H
T
T
φ output
H
kept
kept
kept
kept
kept
kept
T
T
T
T
kept
kept
Rev. 1.00 Mar. 12, 2008 Page 1165 of 1178
Appendix
Program
Execution State
I/O port
Address output
I/O port
I/O port
Address output
I/O port
D15 to D8
I/O port
A15 to A12
I/O port
D7 to D4
I/O port
WR, HWR
Input port
EXCL
φ
I/O port
I/O port
I/O port
D3 to D0
Input port
I/O port
REJ09B0403-0100
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