Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode); Figure 12.19 Sample Serial Reception Flowchart - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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No
Read receive data in RDR and
clear RDRF flag in SSR to 0
No
[3]
Clear ORER flag in SSR to 0
12.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, check that the SCI has finished transmission and the TDRE and TEND flags in SSR
are set to 1, clear the TE bit in SCR to 0, and then set the TE and RE bits to 1 simultaneously with
a single instruction. To switch from receive mode to simultaneous transmit and receive mode,
check that the SCI has finished reception, and clear the RE bit to 0. Then after checking that the
RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, set the TE and
RE bits to 1 simultaneously with a single instruction.
Initialization
Start reception
Read ORER flag in SSR
ORER = 1
No
Error processing
(Continued below)
Read RDRF flag in SSR
RDRF = 1
Yes
All data received?
Yes
Clear RE bit in SCR to 0
<End>
Error processing
Overrun error processing
<End>

Figure 12.19 Sample Serial Reception Flowchart

[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
[2]
If a receive error occurs, read the
ORER flag in SSR, and after
Yes
performing the appropriate error
[3]
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
[4]
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to
1 can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
[5]
Rev. 1.00, 05/04, page 269 of 544

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