Motorola PowerQUICC II MPC8280 Series Reference Manual page 435

dllout
PCI Circuit
PCI Clock
Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock
10.2 External Clock Inputs
The input clock source to the PLL is an external clock oscillator at the bus frequency. The
PLL skew elimination between the CLOCKIN pin and the internal bus clock is guaranteed.
10.3 PLL Pins
Table 10-1 shows the dedicated PLL pins.
Signal
VCCSYN1 Drain Voltage—Analog VDD dedicated to core analog PLL circuits. To ensure core clock stability, filter the
power to the VCCSYN1 input with a circuit similar to the one in "PLL Filtering Circuit" Figure. To filter as
much noise as possible, place the circuit as close as possible to VCCSYN1. The 0.1-µF capacitor should
be closest to VCCSYN1, followed by the 10-µF capacitor, and finally the 10-Ω resistor to Vdd. These
traces should be kept short and direct.
VCCSYN Drain Voltage—Analog VDD dedicated to analog main PLL circuits. To ensure internal clock stability, filter
the power to the VCCSYN input with a circuit similar to the one in "PLL Filtering Circuit" Figure. To filter as
much noise as possible, place the circuit should as close as possible to VCCSYN. The 0.1-µF capacitor
should be closest to VCCSYN, followed by the 10-µF capacitor, and finally the 10-Ω resistor to Vdd.
These traces should be kept short and direct.
VDD
MOTOROLA
Freescale Semiconductor, Inc.
PCI Interface
PCI_CLK
BUS_CLK
DLL
PCI_CLK
clkin2
Table 10-1. Dedicated PLL Pins
10ohm
10uF
Figure 10-4. PLL Filtering Circuit
Chapter 10. Clocks and Power Control
For More Information On This Product,
Go to: www.freescale.com
MPC8280
CPM_CLK
%
Dividers
%
PLL
clkin1
Description
VCCSYN
0.1uF
External Clock Inputs
60x Circuit
60x Bus Clock
10-5