Motorola PowerQUICC II MPC8280 Series Reference Manual page 440

• The memory controller supports the local bus and the 60x bus in parallel. The 60x
bus and the local bus share twelve memory banks as well as two SDRAM machines,
three user-programmable machines (UPMs) and GPCMs.
• The memory controller supports atomic operation.
• The memory controller supports read-modify-write (RMW) data parity check.
• The memory controller supports ECC data check and correction.
• Two data buffer controls (one for the local bus).
• ECC/parity byte select pin, which enables a fast, glueless connection to
ECC/RMW-parity devices.
• 18-bit address and 32-bit local data bus memory controller. The local bus memory
controller supports the following:
— 8-, 16-, and 32-bit port sizes
— Parity checking and generation
— Ability to work in parallel with the 60x bus memory controller
• Flexible chip-select assignment—The 60x bus and local bus share twelve
chip-select lines (controlled by a memory controller bank). The user can allocate the
twelve banks as needed between the 60x bus and the local bus.
• Flexible UPM assignment—The user can assign any of the three UPMs to the 60x
bus or the Local bus
11-2
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MPC8280 PowerQUICC II Family Reference Manual
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