Motorola PowerQUICC II MPC8280 Series Reference Manual page 438

Clock Configuration Modes
10.5.1 Core PLL Configurations
Table 10-4 shows SCMR[CORECNF] bit values and translations to the core PLL mode.
SCMR[CORECNF]
0x04, 0x05, 0x15
10.6 Clock Configuration Modes
The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking
mode is set according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK.
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is
determined by seven bits during the power-on reset—three hardware configuration pins
(MODCK[1–3]) and four bits from hardware configuration word[28–31] (MODCK_H).
Both the PLLs and the dividers are set according to the selected MPC8280 clock operation
mode.
For further information and complete lists of each clock mode's possible clock
configurations, see Section 1.3, "Clock Configuration Modes," in the MPC8280
PowerQUICC II Family Hardware Specifications (order number: MPC8280EC).
10-8
Freescale Semiconductor, Inc.
Table 10-4. 60x Bus-to-Core Frequency
0x06, 0x11
0x08, 0x10
0x0E, 0x1E
0x0A, 0x1A
0x0B, 0x1B
0x0D, 0x1D
0x14
0x03, 0x13
0x0F, 0x1F
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Bus-to-Core Multiplier
2x
2.5x
3x
3.5x
4x
5x
6x
7x
PLL off/bypassed
PLL off
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