Dma Control And Status Registers - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Control and Status Registers

The following registers act as status and control registers for the DMA:
• DMA Status Register –
• DMA Control Registers –
DMA Status Register (DSTAT/DSTATC)
The register allocates a field of three status bits per channel, indicat-
DSTAT
ing whether the channel is currently disabled or active; whether the DMA
has completed or not; and whether an error has been detected. The bits
are read only and a field is cleared by loading the respective
• Active status is set when the DMA channel is enabled (when the
field of the
• DMA completion status is set when the last DMA transaction is
completed.
• Error status is set if an illegal or error condition is detected.
There are three DMA channel status states in which a hardware interrupt
may be generated. These states are reached if one or more of the following
conditions occur:
• Writing to already active DMA channels
• Writing an illegal configuration to DMA channels
(DP register)
• Initializing a DMA channel to read from broadcast memory space
If any of these conditions occur a hardware interrupt is generated if
enabled and the status bits can only be cleared by reading from the
register.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
DSTAT
DCNT
register is set).
DPx
Direct Memory Access
, ,
DCNTST DCNTCL
registers
TCB
register.
TCB
TY
registers
TCB
DSTATC
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