Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 307

Table 8-2. Link Port Register – Group 0x25
Register Number
Reg 0x0 - 3
Reg 0x4 - 7
Reg 0x8 - B
Reg 0xC - F
Reg 0x10 - 13
Reg 0x14 - 17
Reg 0x18 - 1B
Reg 0x1C - 1F
The link transmitter tries to transmit all the data that is written to the
transmit shift register. The link receiver enables data movement only
when the receive shift register is empty. At this point, the received data is
shifted into the receive shift register. After the whole quad-word is
received, the receiver waits until the
data from the shift register to the
is free again, it can enable receiving data again.
DMA
Each link port is associated with two DMA channels. One channel is used
for transmitting data while the other is used for receiving data. The two
DMA channels can interface with either internal or external memory.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Register Quads Links 0-3 Registers
Link # 0 Transmit register
LBUFTX0
Link # 0 Receive register
LBUFRX0
Link # 1 Transmit register
LBUFTX1
Link # 1 Receive register
LBUFRX1
Link # 2 Transmit register
LBUFTX2
Link # 2 Receive register
LBUFRX2
Link # 3 Transmit register
LBUFTX3
Link # 3 Receive register
LBUFRX3
Address
0x1804A0 - 3
0x1804A4 - 7
0x1804A8 - B
0x1804AC - F Read only
0x1804B0 - 3
0x1804B4 - 7
0x1804B8 - B
0x1804BC - F Read only
register is free and copies the
LBUFRx
register. When the shift register
LBUFRx
Link Ports
Remarks
Read only
Read only
8-5