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DSP Architecture
The TigerSHARC processor uses the address on the external port bus to
pipeline the data. This allows interfacing to synchronous DRAM and
speeds up interprocessor accesses. An option allows asynchronous opera-
tion for slower devices.
External data can be accessed by DMA channels or by the core. For core
accesses, the read latency can be significant—eight or more cycles. The
core provides I/O buffering by stalling if the data is accessed before the
data is loaded in a universal register (Ureg).
Programmable memory wait states permit peripherals with different pipe-
line delay cycle, access, hold, and disable time requirements.
External shared memory resources are assigned between processors by
using semaphore operations.
Multiprocessing
The TigerSHARC processor offers features tailored to multiprocessing
systems:
• The unified address space allows direct interprocessor accesses of
each TigerSHARC processor internal memory and resources.
• Distributed bus arbitration logic is included on chip for glueless
connection of systems containing up to eight TigerSHARC proces-
sors and a host processor.
• Bus arbitration rotates, except for host requests that always hold
the highest priority.
• Processor bus lock allows indivisible read-modify-write sequences
for semaphores.
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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