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There are four general-purpose interrupt pins that can be programmed to
be edge- or level-sensitive. When one of these interrupt pins is activated,
an interrupt is issued (if enabled).
Vector Interrupt (VIRPT)
The vector register is:
– interrupt priority 48; edge-triggered
VIRPT
After reset, the vector interrupt is enabled but the vector is not initialized.
This is one of the events that can initiate booting by another master.
Additionally, this interrupt is a general-purpose interrupt for another mas-
ter's use. Another master, either the host or a TigerSHARC processor, can
write an address to this register. The write causes a vector interrupt to
occur. The value that is written into the register is the address of the inter-
rupt routine.
Bus Lock Interrupt
The vector register is:
•
IVBUSLK
After reset, the bus lock interrupt is disabled and vectors are not
initialized.
This interrupt is issued when the bus lock bit in the
and the TigerSHARC processor becomes the bus master. This interrupt is
used to indicate that the TigerSHARC processor has locked the external
bus.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
– interrupt priority 50; edge-triggered
Interrupts
register is set
SQCTL
4-7
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