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Flag Pins
4. After the other TigerSHARC processors receive the indication
from the LPD, they should follow steps 1 to 3, and 5 in the flow for
a single processor system.
5. The LPD now executes steps 4 and 5 in the flow for a single proces-
sor system. This can also run in parallel to step 4 above.
Return to Normal Operation
The TigerSHARC processor returns to operation when it senses a falling
edge on any of the interrupt inputs
causes the TigerSHARC processor to execute the interrupt routine.
In a multiprocessing system, all TigerSHARC processors should be acti-
vated by the interrupt. The LPD wakes up as a master with the bus locked.
It cannot release the bus lock or access the other TigerSHARC processors
until all TigerSHARC processors are active. This can be indicated by the
flag pins.
Flag Pins
There are four input/output flag pins. Each pin can be individually con-
figured to be an input or output. When they are configured as input flag
pins, they can be used either as a condition or as a value in the
ister. (See "Sequencer Status Register – SQSTAT" on page 2-16.) After
power up reset,
them at zero value.
3-8
are inputs where static 100KΩ pull-downs hold
FLAG(3-0)
. The interrupt, if enabled,
IRQ3-0
ADSP-TS101 TigerSHARC Processor
Hardware Reference
reg-
SQSTAT
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