Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 369

code, leaving no trace of itself in TigerSHARC processor internal mem-
ory. When this series of DMA processes completes, the IVT entry of
AutoDMA channel 0 (and AutoDMA channel 1) points to internal mem-
ory address 0, allowing the user's application code to begin execution.
A host must monitor the status of the AutoDMA via the DMA Status reg-
ister to ensure that overrun of the AutoDMA buffer does not occur
DSTAT
during the boot process. Buffer overrun can occur when the boot loader
kernel executes time-consuming memory initializations, which delay ser-
vicing of the host writes to the AutoDMA buffer.
By default, the external bus width is configured to 32-bit width in
upon power up reset, therefore host as bus master must use pipelined pro-
tocol to communicate with the TigerSHARC processor. Please refer to
"TigerSHARC processor Pipelined Interface" on page 6-14 for details on
the pipelined protocol.
The host boot loader kernel provided by Analog Devices with the Visu-
alDSP++ software development tools assumes the processor has been
configured for normal-word transfers. Upon reset, the default state of
AutoDMA is configured for quad-word accesses. In order to use the pro-
ADSP-TS101 TigerSHARC Processor
Hardware Reference
System Design
SYSCON
10-23