Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 31

I/O PROCESSOR
DMA
CONTROLLER
DMA ADDRESS
DMA DATA
CONTROL/
STATUS/
TCBs
Figure 1-2. TigerSHARC I/O Peripherals Diagram
• Program sequencer—Controls the program flow and contains an
instruction alignment buffer (IAB) and a branch target buffer
(BTB)
• Three 128-bit buses providing high bandwidth connectivity
between all blocks
• External port interface including the host interface, SDRAM con-
troller, static pipelined interface, four DMA channels, four link
ports (each with two DMA channels), and multiprocessing support
ADSP-TS101 TigerSHARC Processor
Hardware Reference
INTERNAL MEMORY
MEMORY MEMORY MEMORY
M0 M1 M2
64K X 32 64K X 32 64K X 32
A D A D A
I/O ADDRESS
32 128 128
LINK DATA
Introduction
JTAG PORT
SDRAM CONTROLLER
D
EXTERNAL PORT
M0 ADDR
MULTIPROCESSOR
M0 DATA
INTERFACE
HOST INTERFACE
M1 ADDR
INPUT FIFO
M1 DATA
OUTPUT BUFFER
M2 ADDR
OUTPUT FIFO
M2 DATA
CLUSTER BUS
32
ARBITOR
LINK PORT
CONTROLLER
LINK
PORTS
CONTROL/
STATUS/
BUFFERS
6
32
ADDR
64
DATA
CNTRL
3
L0
8
3
L1 8
3
8
L2
3
8
L3
1-3