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When the TigerSHARC processor boots from a link port, data is trans-
ferred to internal memory per link request. In both of these cases, the
internal memory initial address is 0x00000. DMA channel 0 is used for
EPROM bootstrap and any link receive DMA channel can be used for
link bootstrap. The
registers.
Boot EPROM to Internal Memory
The transmitter
and the receiver
ory. The TigerSHARC processor reads data from an 8-bit EPROM and
moves the data to internal memory. Both
power up reset.
If EPROM boot option is selected, the
the transmitter's
receiver's
TCB DP
ter is detailed in Table 10-5 on page 10-34 and Table 10-6 on
page 10-35.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
fields are reset in all the other channels
TY
is programmed to start reading data from EPROM,
TCB
is programmed to start writing to the internal mem-
TCB
register, and to "Internal Memory" in the
TCB DP
register. Configuration information for the
System Design
s receive their values after
TCB
field is set to "Boot EPROM" in
TY
TCBx DP
regis-
TCB DP
10-33
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