15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-15. DCNT (Lower) Register
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Direct Memory Access
PA0 Pause bit
0 – Continue transferring data
1 – Stop channel # data transfer after
current transaction (if started)
PA1 Pause bit
PA2 Pause bit
PA3 Pause bit
PA4 Pause bit
PA5 Pause bit
PA6 Pause bit
PA7 Pause bit
Reserved
PA8 Pause bit
PA9 Pause bit
PA10 Pause bit
PA11 Pause bit
Reserved
7-27
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