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• A vector interrupt capability is provided for interprocessor
commands.
• Broadcast writes allow simultaneous transmissions of data to all
TigerSHARC processors.
Host Interface
Connecting a host processor to a cluster of TigerSHARC processors is
simplified by the memory-mapped nature of the interface bus and the
availability of special host bus request signals.
A host that is able to access a pipelined memory interface can be easily
connected to the parallel TigerSHARC processor bus. All the internal
memory, Uregs, and resources within the TigerSHARC processor, such as
the DMA control registers and the internal memory, are accessible to the
host.
The host interface is through the TigerSHARC processor external address
and data bus, with additional lines being provided for host control. The
protocol is similar to the standard TigerSHARC processor pipelined bus
protocol.
The host becomes bus master of the cluster by asserting the Host Bus
Request (
) signal. Host Bus Grant (
HBR
SHARC processors when the current master grants bus by asserting
The host interface is synchronous, and can be delayed a number of cycles
to allow slow host access. The host can also access external memory
directly.
All DMA channels are accessible to the host interface, allowing code and
data transfers to be accomplished with low software overhead. The host
can directly read and write the internal memory of the TigerSHARC pro-
cessor and can access the DMA channel setup. Vector interrupt support is
provided for efficient execution of host commands and burst-mode
transfers.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
) is returned by the Tiger-
HBG
Introduction
.
HBR
1-21
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