Multiprocessing - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Multiprocessing

Multiprocessing
The TigerSHARC processor incorporates distributed arbitration logic that
supports multiprocessing. There can be up to eight processors plus a host
connected to the same external bus and each of the bus agents can become
the master of the bus.
The I/O pins that are related to multiprocessing are listed in Table 5-3,
where type may be Input (I), Output (O), or Three-state (T).
Table 5-3. Multiprocessing I/O Pins
Signal Description
Multiprocessing Bus Request Pins
BR7-0
Used by the DSPs in a multiprocessor system to arbitrate for bus mastership. Each Tig-
erSHARC processor drives its own
inputs) and monitors all others. In systems with fewer than eight DSPs, set the unused
pins high.
BRx
Host Bus Request
HBR
A host must assert
When
HBR
and asserts
Host Bus Grant
HBG
Acknowledges
When relinquishing the bus, the master TigerSHARC processor three-states the
ADDR31-0
,
CAS SDWE
mode. The TigerSHARC processor asserts
processing systems, the current bus master TigerSHARC processor drives
slave DSPs monitor
enabled on the TigerSHARC processor with
this pin as either pull-up or no connection. If
pull-up.
5-38
to request control of the TigerSHARC processor external bus.
HBR
is asserted in a multiprocessing system, the bus master relinquishes the bus
once the outstanding transaction is finished.
HBG
and indicates that the host can take control of the external bus.
HBR
, , , ,
DATA63-0 MSH MSSD
, , , and
SDA10 SDCKE LDQM
. The
HBG HBG
line (corresponding to the value of its
BRx
, , , ,
MS1-0 RD WRL WRH BMS
pins and puts the SDRAM into self-refresh
HDQM
until the host deasserts
HBG
pin has an internal pull-up resistor, which is only
2-0 = 0. If
ID ID0
is not used, terminate this pin as
ID7-1
ADSP-TS101 TigerSHARC Processor
2-0
ID
, , , ,
BRST FLYBY IOEN RAS
. In multi-
HBR
while all
HBG
is not used, terminate
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