SDRAM Physical Connection
Table 6-7. Word Page Size 1k, 64-Bit Bus Width
Physical
TigerSHARC
Processor Pin
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
SDA10
A11
A12
A13
A14
A15
6-18
Bank Active Cycle
Column Access Cycle
Internal Address
Internal Address
10
0
11
1
12
2
13
3
14
4
15
5
16
6
17
7
18
8
19
9
20
10
21
Zero
Irrelevant
Irrelevant
22
22
23
23
24
24
25
One
Physical SDRAM Pin
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
NC
A11 or Bank
A12 or Bank
A13 or Bank
A14 or Bank
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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