Multiprocessing Operation - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Multiprocessing Operation

Table 6-10. Data Throughput Rates (Cont'd)
Accesses
Sequential Interrupted
Sequential Uninterrupted
Non-sequential Uninterrupted Write
Sequential Interrupted
Both
Both
Non-sequential
Non-sequential
Autorefresh before read
Autorefresh before write
1 SYSCON external bus width configuration: 64-bit bus
2 With SDRAM buffering (pipeline depth = 1), replace any instance of (CL) with (CL+1)
Multiprocessing Operation
In a multiprocessing environment, the SDRAM is shared among two or
more TigerSHARC processors. SDRAM input signals are always driven by
the bus master. The slave processors track the commands that the master
processor issues to the SDRAM. This feature or function helps to synchro-
nize the SDRAM refresh counters and to prevent needless refreshing
operations.
6-28
Operations Page
Read Same
Write Same
Same
Write Same
Read to Write Same
Write to Read Same
Reads Different 1 word/12 cycles
Writes Different 1 word/6 cycles
Reads Different 1 word/17 cycle
Writes Different 1 word/11 cycle
ADSP-TS101 TigerSHARC Processor
1,2
Throughput per SDRAM Clock
(64-bit words)
1 word/ 8 cycles
(6 + CL)
1 word/1 cycle
1 word/1 cycle
1 word/1 cycle
1 word/6 cycles
1 word/4 cycles
(2 + CL)
(6 + t + t + )
CL
RP RCD
6 + 2(t + t + t + CL)
RP RAS RCD
2 + 2(t + t + t )
RP RAS RCD
Hardware Reference