Dix Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Transfer Control Block Registers
These four registers form a quad-word
quad-word from memory via chaining or by the core. The following con-
ditions apply (note only quad accesses are allowed).
• Loading an inactive
register reinitializes the state of the DMA channel, clearing the
channel status bits to zero. The DMA request counters are flushed
and any internal DMA states are reset.
• Loading an active
an interrupt. The
(DSTAT/DSTATC)" on page 7-23) can be read to determine if
the channel is active.
To initiate a new master DMA sequence after the current one has finished,
the program must write new parameters to the
the DMA (for chained DMA operations, this is done automatically.).
Figure 7-4. TCB Register

DIx Register

This is the 32-bit Index register for the DMA. It can point to the address
of external, internal memory, or link ports.
Figure 7-5. DIx Register
7-16
( field in
TCB TY
into an active channel
TCB
register (see "DMA Status Register
DSTAT
31
DI REGISTER
63
DX REGISTER
95
DY REGISTER
127
DP REGISTER
31
ADDRESS
ADSP-TS101 TigerSHARC Processor
that can be loaded as an aligned
TCB
register = 000) into a
DP
register generates
TCB
registers, re-enabling
TCB
0
32
64
96
0
Hardware Reference
TCB