Link Ports; Miscellaneous; Timers; Clock Domains - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Link Ports

The TigerSHARC processor has four 8-bit link ports that provide addi-
tional I/O capabilities in multiprocessing systems. The link ports have the
following characteristics.
• Link clock speed is selectable as either 1/8, 1/4, 1/3, or 1/2 of
internal clock frequency.
• Link port data is packed into 128-bit words for DMA transfer to
on- or off-chip memory.
• Each link port has its own buffer registers.
• Link port transfers are controlled by clock/acknowledge
handshaking.
• Link ports support bidirectional transfer and flow through and
transfers to/from the external port or other links.

Miscellaneous

Timers

The TigerSHARC processor has two programmable interval timers that
provide periodic interrupt generation. When enabled, the timers decre-
ment a 64-bit count register every cycle. When this count register reaches
zero, the TigerSHARC processor generates an interrupt and asserts
output (for timer zero only). The count register is automatically reloaded
from a 64-bit period register and the count resumes immediately.

Clock Domains

There are two major clock domains in the TigerSHARC processor, driven
by two input clocks—the local clock (
ADSP-TS101 TigerSHARC Processor
Hardware Reference
) and the system clock (
LCLK
Introduction
TMR0E
).
SCLK
1-23