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processors in the idle state at startup allows the TigerSHARC processor
with
=
ID2–0
000
SHARC processor with
remaining processors by writing to their AutoDMA channel 0 buffers via
multiprocessor memory space.
An example system that uses this "one-boots-others" technique appears in
Figure 10-6.
ADSP-TS101
VDDIO
BMS
ADSP-TS101
VDDIO
BMS
ADSP-TS101
Figure 10-6. Sequential Booting from an EPROM
ADSP-TS101 TigerSHARC Processor
Hardware Reference
to become bus master and boot itself. When Tiger-
=
ID2–0
000
ADDR31-0
DATA63-0
RD
ACK
BMS
(S0)
ADDR31-0
DATA63-0
RD
ACK
(S1)
ADDR31-0
DATA63-0
RD
ACK
(S7)
has finished booting, it can boot the
ADDR23-0
DATA7-0
System Design
ADDR
DATA
RD
8-BIT
CS
EPROM
10-29
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