Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 255

Table 7-1. DPx Register Bit Descriptions (Cont'd)
Bit Description
Chaining Enabled
CHEN
Bit22 0 – No Chaining
1 – DMA loads chaining targets channel
This bit disables chaining or enables chaining. If set the DMA loads the chaining
destination channel
the
CHPT
DMA Request Enable
DRQ
Bit23 0 – Once the DMA channel is enabled, the whole block is transferred
1 – DMA issues transactions only upon request
If cleared (=0) this bit disables the functionality of the
DMA transfers. This results in the entire block of data being transferred once the
TCB
If enabled (=1) this bit results in external port transactions occurring only upon a
request signaled on the
For AutoDMA channels this bit must always be set.
Interrupt Enable
INT
Bit24 0 – DMA interrupt is disabled
1 – The DMA interrupts the core after transferring the whole block
If cleared (=0) this bit disables the generation of an interrupt on completion of the
DMA block transfer.
When enabled (=1) an interrupt is generated upon completion of the DMA. The
interrupt is generated when the count field of the DMA channels
zero.
Operand Length
LEN
Bits26–25 00 – Reserved
01 – Normal (32-bit) word
10 – Long (64-bit) word
11 – Quad (128-bit) word
These bits specify the length of the operand to be transferred on each DMA transac-
tion. The original source or destination address specified in the
aligned to a word boundary as specified with the setting of these bits. Thus if oper-
and length is set to quad, then the address originally loaded in the
be divisible by four.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
registers from the internal memory location pointed to by
TCB
and fields.
MS
registers have been written to.
DMARx
Direct Memory Access
registers from internal memory
TCB
pins.
pins on external port
DMARx
decrements to
TCB
register must be
DIx
register must
DIx
7-21