Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 30

COMPUTATIONAL BLOCKS
SHIFTER
ALU
MULTIPLIER
X
REGISTER
FILE
32x32
128
DAB
DAB
128
Y
REGISTER
FILE
32x32
MULTIPLIER
ALU
SHIFTER
Figure 1-1. TigerSHARC Core Diagram
As shown in Figure 1-1 and Figure 1-2, the processor has the following
architectural features:
• Dual computation blocks—X and Y—each consisting of a multi-
plier, ALU, shifter, and a 32-word register file
• Dual integer ALUs—J and K—each containing a 32-bit IALU and
32-word register file
1-2
PROGRAM SEQUENCER
PC BTB IRQ
ADDR
IAB
FETCH
128
128
DATA ADDRESS GENERATION
32
INTEGER
J-IALU
32X32
32
128
32
128
32
128
ADSP-TS101 TigerSHARC Processor
Hardware Reference
32
INTEGER
K-IALU
32X32