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IOP Registers
Chain pointer registers. Shown in
the TCB (parameter register values) for the next DMA operation on the
corresponding channel. These registers also control whether the I/O pro-
cessor generates an interrupt when the current DMA process ends.
Table 2-5. Chain Pointer Registers
Register Name
CPSP0–5A
CPSP0–5B
CPSPI
CPSPIB
CPPP
Standard DMA Status Registers
The registers shown in
DMA status registers.
Table 2-6. Standard DMA Status Registers
Register Name
PPCTL
SPMCTLxy
SPIDMAC
SPIDMACB
2-8
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Table
Width (Bits) Description
29
SPORTA
29
SPORTB
20
SPI
20
SPIB
20
Parallel Port
Table 2-6
provide information on the standard
Width (Bits) Description
32
Parallel port control register
32
SPORT Multichannel Control Registers
32
SPI DMA control
32
SPIB DMA control
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
2-5, hold the starting address of
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