Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 314

Link Port Communication Protocol
LxCLKOUT
LxCLKIN
LxDAT7:0
Figure 8-6. Quad-word Completion and a
New Quad-word Beginning When
If is set high before the 12th edge, there back-to-back transmis-
LxCLKIN
sions occur.
NEXT TRANSFER NO
ACKNOWLEDGE
LxCLKOUT
LxCLKINB
LxDAT7:0
Figure 8-7. Transfer Waits Because Receiver Buffer is Full
8-12
CONNECTIVI TY
CHECK
B0 B1 B2 B3 B4
TRAN SMI TT ER WAITS FOR
LXCLKIN SET
B2 B3
N EXT TRANSFER
ACKNOWLEDGE
B5 B13
Bit is Cleared
VERE
NEXT TRANSFER
ACKNOWL EDGE
B15
ADSP-TS101 TigerSHARC Processor
NEXT TRANSFER
BEGIN S
B14 B15 B0 B1
NEXT TRANSFER
BEGINS
B0 B1 B2
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