Table of Contents
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Enabling and Disabling Chaining
7-42
Ending a DMA Sequence 7-49
enhanced communications regis-
ters 2-13
Entering Low Power Mode 3-6
EP Channels (0 to 3) Type Restric-
tions 7-30
EPROM Boot
EPROM TCB 10-34
Internal Memory TCB 10-35
EPROM boot (BMS) 3-1, 4-2, 5-5,
10-8, 10-32–10-34
EPROM Interface 5-31
EPROM interface 5-3, 5-31–5-33
EPROM TCB 10-34
EPROM/Flash Device Boot 10-20
EPROM/flash device boot 10-20
Error Detection Mechanisms 8-17
exception
(software
2-21, 4-3, 4-9–4-10, 4-16, 4-23–
4-25
Exceptions 4-23
external bus 1-19, 5-1–5-51, 7-7–
7-8
External Bus and Host Interface
1-19
External Bus Features 5-2
External I/O Device to External
Memory (Flyby) 7-55
External Memory 1-19
external memory 1-19, 1-21, 1-22,
2-2, 2-4–2-5, 5-3, 5-9, 7-54, 7-67
External Memory Bank Space 2-4
ADSP-TS101 TigerSHARC Processor
Hardware Reference
interrupt)
External Memory Bank Space
2-5
External Memory DMA 7-67
External Memory TCB 7-52, 7-56
External Memory TCB (Flyby)
7-58, 7-60
External Memory to External I/O
Device (Flyby) 7-57
External Multiprocessor Space 2-6
External Port 1-19
external port 1-19–1-21, 1-23,
2-47, 5-7, 7-13, 7-28, 7-37, 7-38,
7-50–7-62, 7-63, 7-67, 10-8
External Port Configuration and
Status Registers 2-41
External Port Configuration and
Status Registers 2-41
External Port DMA 7-50
External Port DMA Control 7-32
External Port DMA Register 2-43
External Port DMA Register 2-43
External Port DMA Transfer
Types 7-51
External Port Registers 2-30
External to Internal Memory 7-51
F
FFT algorithms 1-13
fixed-point formats 1-8
FLAG (Flag pins) 3-8
Flag Pins 3-8
Flash memory interface 5-3, 5-33
Flyby (FLYBY) 5-3, 5-5, 5-34–
5-37, 7-8, 7-55–7-57
INDEX
vii
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