Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 180

Multiprocessing
own . Then, bus mastership is passed to the new requester. The new bus
BR
master retains the bus mastership by maintaining its
continuously. When the current master relinquishes the bus, it is assigned
the lowest priority. When other slaves want to become masters, each of
them asserts their own
mastership of the bus. The remaining competing slaves keep their
asserted until gaining bus mastership according to their priority. There is
no pipeline between masters. The current master completes all its pending
transactions (transactions that have begun executing on the cluster bus)
before relinquishing the bus. Because of master change cycles, an IDLE
cycle occurs when mastership is passed from the current master to a new
master.
TS0 IS THE
MASTER
SCLK
BR0
BR1
BR2
CPA
DPA
HBR
Figure 5-20. External Bus Arbitration Sequence,
5-42
and the slave with the highest priority gains the
BR
TURN
OVER
TS1 IS THE
CYCLE
MASTER
BR
TURN
OVER
TS2 IS THE
CYCLE
MASTER
/
CPA DPA
ADSP-TS101 TigerSHARC Processor
, which is asserted
s
BR
TURN
OVER
TS0 IS THE
CYCLE
MASTER
/ Inactive
HBR
Hardware Reference