Performance Monitor Counter - Prfcnt; Performance Monitor Mask - Prfm - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Table 2-13. Debug Register Groups for 0x3E Register Numbers
Register Name
TRCB0
TRCB1
TRCB2
TRCB3
TRCB4
TRCB5
TRCB6
TRCB7
Performance Monitor Counter – PRFCNT
The purpose of the performance counter is to register the cycle where
monitored conditions occur. The monitored condition is identified by the
performance monitor mask register (
reset.
Performance Monitor Mask – PRFM
The performance monitor identifies which of the following events is
counted by the performance monitor counter (
which events are monitored and Bit31 indicates if the events in the same
cycle are summed or ORed. The entire register is cleared after reset. The
bit descriptions for this register are shown in Figure 2-2 on page 2-24 and
Figure 2-3 on page 2-25.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Register Type Direct Memory Address
Trace buffer 0 0x1807C0
Trace buffer 1 0x1807C1
Trace buffer 2 0x1807C2
Trace buffer 3 0x1807C3
Trace buffer 4 0x1807C4
Trace buffer 5 0x1807C5
Trace buffer 6 0x1807C6
Trace buffer 7 0x1807C7
Memory and Register Map
Remarks
Read only, reset value 0x0
Read only, reset value 0x0
Read only, reset value 0x0
Read only, reset value 0x0
Read only, reset value 0x0
Read only, reset value 0x0
Read only, reset value 0x0
Read only, reset value 0x0
). The register is cleared after
PRFM
). Bits30–0 indicate
PRFCNT
2-23