Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 150

SYSCON Programming
MULTIPROCESSING BUS WIDTH
EXTERNAL MEMORY BUS WIDTH
HOST SLOW PROTOCOL BIT
1 – Slow protocol active,
0 – Synchronous and pipelined
HOST PIPELINE DEPTH BITS
00 – One cycle pipeline depth
01 – Two cycles pipeline depth
10 – Three cycles pipeline depth
11 – Four cycles pipeline depth
Figure 5-3. SYSCON (Upper) Register Bit Descriptions
5-12
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
HOST BUS WIDTH
0 – 32-bits, 1 – 64-bits
0 – 32-bits, 1 – 64-bits
0 – 32-bits, 1 – 64-bits
Reserved
(if slow bit is cleared)
Bit 15 continued on
Figure 5-4
ADSP-TS101 TigerSHARC Processor
Hardware Reference