Internal Memory Dma - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Internal Memory DMA

The DMA channels and I/O devices arbitrate for access to the Tiger-
SHARC processor's internal memory and buses. The DMA controller
determines, on a cycle-by-cycle basis, which channel is allowed access to
the three internal buses or OFIFO, and consequently which channel reads
or writes to internal memory. The priority of the DMA channels is dis-
cussed in "DMA Channel Prioritization" on page 7-36.
There is no overall throughput loss in switching between channels. Any
combination of link ports and external port transfers has the same maxi-
mum internal transfer rate, which is one DMA transfer per cycle.
!
The internal memory clock rate and bus widths are at least twice
the external port clock rate and bus width. Thus the bandwidth of
each internal bus is at least four times greater than the external port
bandwidth.
In the case of link ports, assuming all the links operate at half the
core frequency, the maximum link port bandwidth is 1/16 of an
internal bus bandwidth.
External Memory DMA
When the DMA transfer is between the TigerSHARC processor internal
memory and external memory, the external memory may have one or
more wait states. External memory wait states, however, do not reduce the
overall internal DMA transfer rate if other channels have data available to
transfer. The TigerSHARC processor internal data buses are not held up
by an incomplete external transfer.
When data is to be transferred from internal to external memory, the
internal memory data is placed in the external port's OFIFO, completing
the OFIFO write request. The external memory access then begins inde-
pendently. For external-to-internal DMA, the internal bus DMA request
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Direct Memory Access
7-67