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self-refresh mode and returns it to self-refresh mode before relinquishing
the bus to the TigerSHARC processor. Before entering into self-refresh
mode, the same conditions that apply to the refresh mode (see "Refresh
(REF) Command" on page 6-42) must be sustained. Similarly, reaccessing
the SDRAM after exiting from self-refresh mode is also limited by the
same restrictions as for refresh mode. Self-refresh mode is entered by deas-
serting the
SDCKE
The
command causes refresh operations to be performed internally
SREF
by the SDRAM without any external control. Before executing the
command, the SDRAM precharges the active bank. After executing an
exit command, the controller waits t
SREF
refresh cycle. After, the auto refresh command, the SDRAM controller
waits for t
number of cycles before executing a bank active command
XSR
(
).
ACT
Table 6-17. Pin State During REF Command
Pin
MSSD
CAS
RAS
SDWE
SDCKE
Programming Example
This section provides a programming example written for the Tiger-
SHARC processor. The example shown in Listing 6-1 on page 6-44
demonstrates how to set up the SDRAM controller to work with the
ADSP-TS101 EZ-KIT Lite™.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
signal and is exited by reasserting the same signal.
State
low
low
low
high
low
SDRAM Interface
= t
+ t
to execute an auto
XSR
RC
RP
SREF
6-43
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