Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 128

Interrupt Service
5. The TigerSHARC processor mode is changed to emulation mode if
there was an emulation exception; otherwise it changes to supervi-
sor mode.
6. When the first instruction in the interrupt routine reaches EX2 and
if the interrupt is edge-triggered, the corresponding interrupt bit in
the
ILAT
set. The interrupt bit in
interrupt is level-sensitive. Bit60 of
interrupts, but not in the case of an exception or emulation excep-
tion. When the interrupt bit in
hardware interrupts until the
A software interrupt occurs only when the instruction that caused it
reaches pipeline stage EX2. When a software interrupt that was enabled
occurs, all the instructions in the pipeline after the instruction that caused
the exception are aborted, including hardware interrupt routine instruc-
tions. If a software interrupt occurs during the time that the hardware
interrupt is in the pipeline, the hardware interrupt is aborted with other
instructions in the pipeline and the software interrupt procedure begins.
The hardware interrupt flag is not reset, however, in order to save the
(hardware) interrupt.
The hardware ISR steps, illustrated and numbered in Figure 4-1 on
page 4-17, are as follows.
1. Determine state after hardware interrupt (
AND
PMASK_RN
2. Once masks are set:
•
PMASK60
then
• Exceptions and emulation conditions are not affected by
PMASK60
• Insert ISR fetch address
4-16
register is reset and the same bit in the
PMASK
AND NOT
is embedded in
= 0...0
PMASK_R50–0
or
IMASK60
is set in any case, not just when the
is set only for hardware
PMASK
is set, it also disables all
PMASK
register is saved.
RETI
IMASK60
.
IMASK60
, that is, if
PMASK_R
ADSP-TS101 TigerSHARC Processor
register is
PMASK
AND
IMASKN
is set
PMASK60
Hardware Reference