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SDRAM Controller Commands
Write Command
A
command is preceded by an
Write
to the page. In
enable the SDRAM to latch the column address to set the burst start
address.
The delay between
parameter. Data is driven by the TigerSHARC processor on the
command.
Single write transactions take a different number of cycles according to
transaction size and external bus width.
• Single-word write – 1 cycle
• Long write on 64-bit bus – 1 cycle
• Long write on 32-bit bus – 2 cycles
• Quad write on 64-bit bus – 2 cycles
• Quad write on 32-bit bus – 4 cycles
If no new command is issued to the SDRAM after a
issued, the SDRAM continues writing to sequential addresses. This is
called 'page mode' or 'burst'. If the whole transaction is more than one
cycle—for example, quad write on a 32-bit bus—no new command is
issued to the SDRAM and the rest of the data is written to sequential
addresses. When the whole transaction is completed, the SDRAM can
continue in different ways:
• If there is no new SDRAM transaction,
followed by a precharge command closing the active page.
• If there is an SDRAM write transaction to the same page, a new
transaction begins on the next cycle.
6-38
commands,
Write
and
ACT
Write
command if it is the first access
ACT
,
, and
CAS
SDWE
MSSD
commands is determined by the t
Bstop
ADSP-TS101 TigerSHARC Processor
are asserted to
RCD
Write
command is
Write
command is issued,
Hardware Reference
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