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static condition flags are grouped into the
ADSP-TS101 TigerSHARC Processor Programming Reference for informa-
tion about how this register is updated and used).
ILAT Registers
The
register is a single 64-bit register accessed as two 32-bit registers
ILAT
and
ILATH
ILATL
occurs, the corresponding bit is set. The interrupt bits order is set accord-
ing to the interrupt priority—bit 0 having lowest priority.
The
register can be written through the set (
ILAT
clear (
ILATCLL
the
register to the OR of the old and written values. As a result, every
ILAT
set bit in the written data is set the corresponding bit in the
Writing to the clear address will AND the data written with the old data
of the
register. In this case, a zero bit in the input data clears the cor-
ILAT
responding bit in
consequences and restrictions of these accesses are detailed in "ILAT Reg-
ister" on page 4-11.
IMASK Register
The
register is a single 64-bit register accessed as two 32-bit regis-
IMASK
ters,
and
IMASKL
The initial value of
0x9001006 1E3C3C000 – Normal reset
0x90011E6 1E3C3C000 – Reset with
PMASK Register
The
register is a single 64-bit register that is accessed as two 32-bit
PMASK
registers,
PMASKL
ADSP-TS101 TigerSHARC Processor
Hardware Reference
. Each bit is dedicated to an interrupt. When an interrupt
or
) addresses. Writing to the set addresses updates
ILATCLH
, while a set bit keeps it unchanged. The
ILAT
.
IMASKH
after reset is:
IMASK
and
. The initial value of
PMASKH
Memory and Register Map
register. (See the
SFREG
or
ILATSTL
enable strap active
IRQ
after reset is 0x0.
PMASK
) and
ILATSTH
register.
ILAT
2-19
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