Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 367

The boot loader kernel then brings in the application code and data
through a series of single-word DMA transfers. Finally, the boot loader
kernel overwrites itself with the application code, leaving no trace of itself
in TigerSHARC processor internal memory. When this DMA process
completes, the IVT entry of DMA channel 0 points to internal memory
address 0, allowing the user's application code to begin execution.
EPROM booting automatically uses a special 8- to 32-bit packing mode,
least-significant-word first, to perform DMA reads from EPROM. Only
DMA channel 0 supports this special packing mode so it must be used to
boot from EPROM. Data is transferred over the data bus pins 7-0 (
). The lowest address pins of the TigerSHARC processor should be con-
0
nected to the EPROM's address lines. The EPROM's chip select should
be connected to
Maximum EPROM address space supported is 16 Mbytes. Refer to
Figure 10-4 on page 10-22.
In a multiprocessor system, the
SHARC processor bus master. This allows wire OR'ing of multiple
signals for a single common boot EPROM.
!
The TigerSHARC processor does not implement automatic pack-
ing when writing to boot EPROM/flash memory space. Therefore
the user must perform manual 32- to 8-bit unpacking when writing
to flash. Access to
accesses are not possible.
For more information, see "Boot EPROM to Internal Memory" on
page 10-33 and "EPROM Interface" on page 5-31.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and its output enable should be connected to
BMS
BMS
memory space is only allowed via DMA; core
BMS
output is only driven by the Tiger-
System Design
DATA7–
.
RD
BMS
10-21